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f5d9036758
Add support for the AArch64 .cpu directive. This is a slightly involved directive since the parameter is actually a variable encoded string. The general structure is: <cpu>[[+-]<feature>]* We now map some of the supported string names for features for internal representation of feature flags. If we encounter one which we do not support, bail out as we cannot validate the assembly any longer. Resolves PR27010. llvm-svn: 265240
64 lines
1.1 KiB
ArmAsm
64 lines
1.1 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-unknown-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s
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.cpu generic
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fminnm d0, d0, d1
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.cpu generic+fp
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fminnm d0, d0, d1
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.cpu generic+nofp
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fminnm d0, d0, d1
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.cpu generic+simd
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addp v0.4s, v0.4s, v0.4s
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.cpu generic+nosimd
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addp v0.4s, v0.4s, v0.4s
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.cpu generic+crc
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crc32cx w0, w1, x3
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.cpu generic+nocrc
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crc32cx w0, w1, x3
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.cpu generic+crypto+nocrc
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aesd v0.16b, v2.16b
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.cpu generic+nocrypto+crc
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aesd v0.16b, v2.16b
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// NOTE: the errors precede the actual output! The errors appear in order
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// though, so validate by hoisting them to the top and preservering relative
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// ordering
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// CHECK: error: instruction requires: fp-armv8
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// CHECK: fminnm d0, d0, d1
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// CHECK: ^
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// CHECK: error: instruction requires: neon
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// CHECK: addp v0.4s, v0.4s, v0.4s
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// CHECK: ^
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// CHECK: error: instruction requires: crc
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// CHECK: crc32cx w0, w1, x3
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// CHECK: ^
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// CHECK: error: instruction requires: crypto
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// CHECK: aesd v0.16b, v2.16b
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// CHECK: ^
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// CHECK: fminnm d0, d0, d1
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// CHECK: fminnm d0, d0, d1
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// CHECK: addp v0.4s, v0.4s, v0.4s
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// CHECK: crc32cx w0, w1, x3
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// CHECK: aesd v0.16b, v2.16b
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