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3262b6a145
xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=x86
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; RUN: llc -pre-RA-sched=source < %s -mtriple=i686-unknown-linux -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED
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; PR2748
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@g_73 = external global i32 ; <i32*> [#uses=1]
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@g_5 = external global i32 ; <i32*> [#uses=1]
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define i32 @func_44(i16 signext %p_46) nounwind {
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entry:
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; SOURCE-SCHED: subl
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; SOURCE-SCHED: movl
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; SOURCE-SCHED: sarl
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; SOURCE-SCHED: xorl
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; SOURCE-SCHED: cmpl
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; SOURCE-SCHED: setg
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; SOURCE-SCHED: movb
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; SOURCE-SCHED: xorl
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; SOURCE-SCHED: subl
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; SOURCE-SCHED: testb
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; SOURCE-SCHED: jne
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%0 = load i32, i32* @g_5, align 4 ; <i32> [#uses=1]
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%1 = ashr i32 %0, 1 ; <i32> [#uses=1]
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%2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]
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%3 = zext i1 %2 to i32 ; <i32> [#uses=1]
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%4 = load i32, i32* @g_73, align 4 ; <i32> [#uses=1]
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%5 = zext i16 %p_46 to i64 ; <i64> [#uses=1]
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%6 = sub i64 0, %5 ; <i64> [#uses=1]
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%7 = trunc i64 %6 to i8 ; <i8> [#uses=2]
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%8 = trunc i32 %4 to i8 ; <i8> [#uses=2]
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%9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
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br i1 %9, label %bb11, label %bb12
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bb11: ; preds = %entry
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%10 = urem i8 %7, %8 ; <i8> [#uses=1]
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br label %bb12
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bb12: ; preds = %bb11, %entry
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%.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ] ; <i8> [#uses=1]
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%11 = icmp ne i8 %.014.in, 0 ; <i1> [#uses=1]
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%12 = zext i1 %11 to i32 ; <i32> [#uses=1]
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%13 = tail call i32 (...) @func_48( i32 %12, i32 %3, i32 0 ) nounwind ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @func_48(...)
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