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16c1c3ddfc
"insert_subreg, subreg_to_reg, and reg_sequence" instructions' after adjusting some unittest checks. This is to solve PR28852. The restriction was added at 2010 to make better register coalescing. We assumed that it was not necessary any more. Testing results on x86 supported the assumption. We will look closely to any performance impact it will bring and will be prepared to help analyzing performance problem found on other architectures. Differential Revision: https://reviews.llvm.org/D23210 llvm-svn: 278466
317 lines
10 KiB
LLVM
317 lines
10 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false -fixup-byte-word-insts=1 \
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; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL -check-prefix=BWON
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false -fixup-byte-word-insts=0 \
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; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL -check-prefix=BWOFF
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false -fixup-byte-word-insts=1 \
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; RUN: | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C -check-prefix=BWON
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; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr +sse2 -asm-verbose=false -fixup-byte-word-insts=0 \
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; RUN: | FileCheck %s -check-prefix=CHECK-I686
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define void @test_load_store(half* %in, half* %out) {
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; CHECK-LABEL: test_load_store:
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; BWON: movzwl (%rdi), %eax
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; BWOFF: movw (%rdi), %ax
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; CHECK: movw %ax, (%rsi)
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%val = load half, half* %in
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store half %val, half* %out
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ret void
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}
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define i16 @test_bitcast_from_half(half* %addr) {
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; CHECK-LABEL: test_bitcast_from_half:
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; BWON: movzwl (%rdi), %eax
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; BWOFF: movw (%rdi), %ax
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%val = load half, half* %addr
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%val_int = bitcast half %val to i16
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ret i16 %val_int
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}
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define void @test_bitcast_to_half(half* %addr, i16 %in) {
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; CHECK-LABEL: test_bitcast_to_half:
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; CHECK: movw %si, (%rdi)
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%val_fp = bitcast i16 %in to half
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store half %val_fp, half* %addr
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ret void
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}
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define float @test_extend32(half* %addr) {
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; CHECK-LABEL: test_extend32:
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; CHECK-LIBCALL: jmp __gnu_h2f_ieee
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; CHECK-F16C: vcvtph2ps
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to float
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ret float %val32
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}
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define double @test_extend64(half* %addr) {
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; CHECK-LABEL: test_extend64:
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: cvtss2sd
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtss2sd
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to double
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ret double %val32
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}
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define void @test_trunc32(float %in, half* %addr) {
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; CHECK-LABEL: test_trunc32:
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-F16C: vcvtps2ph
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%val16 = fptrunc float %in to half
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store half %val16, half* %addr
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ret void
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}
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define void @test_trunc64(double %in, half* %addr) {
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; CHECK-LABEL: test_trunc64:
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; CHECK-LIBCALL: callq __truncdfhf2
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; CHECK-F16C: callq __truncdfhf2
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%val16 = fptrunc double %in to half
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store half %val16, half* %addr
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ret void
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}
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define i64 @test_fptosi_i64(half* %p) #0 {
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; CHECK-LABEL: test_fptosi_i64:
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; CHECK-LIBCALL-NEXT: pushq %rax
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; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
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; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, %rax
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; CHECK-LIBCALL-NEXT: popq %rcx
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; CHECK-LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvttss2si [[REG2]], %rax
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; CHECK-F16C-NEXT: retq
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%a = load half, half* %p, align 2
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%r = fptosi half %a to i64
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ret i64 %r
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}
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define void @test_sitofp_i64(i64 %a, half* %p) #0 {
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; CHECK-LABEL: test_sitofp_i64:
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; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z]+]]
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; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
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; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, %xmm0
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; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
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; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
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; CHECK_LIBCALL-NEXT: popq [[ADDR]]
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; CHECK_LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG0:%[a-z0-9]+]], [[REG0]]
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; CHECK-F16C-NEXT: vcvtps2ph $4, [[REG0]], [[REG0]]
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; CHECK-F16C-NEXT: vmovd [[REG0]], %eax
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; CHECK-F16C-NEXT: movw %ax, (%rsi)
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; CHECK-F16C-NEXT: retq
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%r = sitofp i64 %a to half
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store half %r, half* %p
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ret void
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}
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define i64 @test_fptoui_i64(half* %p) #0 {
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; CHECK-LABEL: test_fptoui_i64:
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; FP_TO_UINT is expanded using FP_TO_SINT
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; CHECK-LIBCALL-NEXT: pushq %rax
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; CHECK-LIBCALL-NEXT: movzwl (%rdi), %edi
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; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-NEXT: movss {{.[A-Z_0-9]+}}(%rip), [[REG1:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: movaps %xmm0, [[REG2:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: subss [[REG1]], [[REG2]]
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; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: movabsq $-9223372036854775808, [[REG4:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: xorq [[REG3]], [[REG4]]
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; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, [[REG5:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: ucomiss [[REG1]], %xmm0
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; CHECK-LIBCALL-NEXT: cmovaeq [[REG4]], [[REG5]]
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; CHECK-LIBCALL-NEXT: popq %rcx
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; CHECK-LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovss {{.[A-Z_0-9]+}}(%rip), [[REG3:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vsubss [[REG3]], [[REG2]], [[REG4:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvttss2si [[REG4]], [[REG5:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: movabsq $-9223372036854775808, [[REG6:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: xorq [[REG5]], [[REG6:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvttss2si [[REG2]], [[REG7:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vucomiss [[REG3]], [[REG2]]
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; CHECK-F16C-NEXT: cmovaeq [[REG6]], %rax
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; CHECK-F16C-NEXT: retq
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%a = load half, half* %p, align 2
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%r = fptoui half %a to i64
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ret i64 %r
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}
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define void @test_uitofp_i64(i64 %a, half* %p) #0 {
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; CHECK-LABEL: test_uitofp_i64:
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; CHECK-LIBCALL-NEXT: pushq [[ADDR:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: movq %rsi, [[ADDR]]
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; CHECK-NEXT: testq %rdi, %rdi
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; CHECK-NEXT: js [[LABEL1:.LBB[0-9_]+]]
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; simple conversion to float if non-negative
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; CHECK-LIBCALL-NEXT: cvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG1:%[a-z0-9]+]], [[REG1]]
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; CHECK-NEXT: jmp [[LABEL2:.LBB[0-9_]+]]
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; convert using shift+or if negative
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; CHECK-NEXT: [[LABEL1]]:
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shrq %rax
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: orq %rax, [[REG2:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: cvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]]
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; CHECK-LIBCALL-NEXT: addss [[REG3]], [[REG1]]
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; CHECK-F16C-NEXT: vcvtsi2ssq [[REG2]], [[REG3:%[a-z0-9]+]], [[REG3]]
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; CHECK-F16C-NEXT: vaddss [[REG3]], [[REG3]], [[REG1:[%a-z0-9]+]]
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; convert float to half
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; CHECK-NEXT: [[LABEL2]]:
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; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
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; CHECK-LIBCALL-NEXT: movw %ax, ([[ADDR]])
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; CHECK-LIBCALL-NEXT: popq [[ADDR]]
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; CHECK-F16C-NEXT: vcvtps2ph $4, [[REG1]], [[REG4:%[a-z0-9]+]]
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; CHECK-F16C-NEXT: vmovd [[REG4]], %eax
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; CHECK-F16C-NEXT: movw %ax, (%rsi)
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; CHECK-NEXT: retq
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%r = uitofp i64 %a to half
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store half %r, half* %p
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ret void
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}
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define <4 x float> @test_extend32_vec4(<4 x half>* %p) #0 {
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; CHECK-LABEL: test_extend32_vec4:
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C: vcvtph2ps
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%a = load <4 x half>, <4 x half>* %p, align 8
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%b = fpext <4 x half> %a to <4 x float>
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ret <4 x float> %b
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}
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define <4 x double> @test_extend64_vec4(<4 x half>* %p) #0 {
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; CHECK-LABEL: test_extend64_vec4
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; CHECK-LIBCALL: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-DAG: cvtss2sd
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; CHECK-LIBCALL-DAG: cvtss2sd
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; CHECK-LIBCALL-DAG: cvtss2sd
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; CHECK-LIBCALL: cvtss2sd
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; CHECK-F16C: vcvtph2ps
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; CHECK-F16C-DAG: vcvtph2ps
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; CHECK-F16C-DAG: vcvtph2ps
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; CHECK-F16C-DAG: vcvtph2ps
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; CHECK-F16C-DAG: vcvtss2sd
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; CHECK-F16C-DAG: vcvtss2sd
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; CHECK-F16C-DAG: vcvtss2sd
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; CHECK-F16C: vcvtss2sd
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%a = load <4 x half>, <4 x half>* %p, align 8
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%b = fpext <4 x half> %a to <4 x double>
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ret <4 x double> %b
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}
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define void @test_trunc32_vec4(<4 x float> %a, <4 x half>* %p) {
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; CHECK-LABEL: test_trunc32_vec4:
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-LIBCALL: callq __gnu_f2h_ieee
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; CHECK-F16C: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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; CHECK-F16C: vcvtps2ph
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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%v = fptrunc <4 x float> %a to <4 x half>
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store <4 x half> %v, <4 x half>* %p
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ret void
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}
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define void @test_trunc64_vec4(<4 x double> %a, <4 x half>* %p) {
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; CHECK-LABEL: test_trunc64_vec4:
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; CHECK: callq __truncdfhf2
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; CHECK: callq __truncdfhf2
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; CHECK: callq __truncdfhf2
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; CHECK: callq __truncdfhf2
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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; CHECK: movw
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%v = fptrunc <4 x double> %a to <4 x half>
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store <4 x half> %v, <4 x half>* %p
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ret void
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}
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declare float @test_floatret();
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; On i686, if SSE2 is available, the return value from test_floatret is loaded
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; to f80 and then rounded to f32. The DAG combiner should not combine this
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; fp_round and the subsequent fptrunc from float to half.
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define half @test_f80trunc_nodagcombine() #0 {
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; CHECK-LABEL: test_f80trunc_nodagcombine:
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; CHECK-I686-NOT: calll __truncxfhf2
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%1 = call float @test_floatret()
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%2 = fptrunc float %1 to half
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ret half %2
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}
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; CHECK-LABEL: test_sitofp_fadd_i32:
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; CHECK-LIBCALL-NEXT: pushq %rbx
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; CHECK-LIBCALL-NEXT: subq $16, %rsp
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; CHECK-LIBCALL-NEXT: movl %edi, %ebx
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; CHECK-LIBCALL-NEXT: movzwl (%rsi), %edi
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; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-NEXT: movss %xmm0, 12(%rsp)
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; CHECK-LIBCALL-NEXT: cvtsi2ssl %ebx, %xmm0
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; CHECK-LIBCALL-NEXT: callq __gnu_f2h_ieee
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; CHECK-LIBCALL-NEXT: movzwl %ax, %edi
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; CHECK-LIBCALL-NEXT: callq __gnu_h2f_ieee
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; CHECK-LIBCALL-NEXT: addss 12(%rsp), %xmm0
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; CHECK-LIBCALL-NEXT: addq $16, %rsp
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; CHECK-LIBCALL-NEXT: popq %rbx
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; CHECK-LIBCALL-NEXT: retq
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; CHECK-F16C-NEXT: movswl (%rsi), %eax
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; CHECK-F16C-NEXT: vmovd %eax, %xmm0
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; CHECK-F16C-NEXT: vcvtph2ps %xmm0, %xmm0
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; CHECK-F16C-NEXT: vcvtsi2ssl %edi, %xmm1, %xmm1
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; CHECK-F16C-NEXT: vcvtps2ph $4, %xmm1, %xmm1
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; CHECK-F16C-NEXT: vcvtph2ps %xmm1, %xmm1
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; CHECK-F16C-NEXT: vaddss %xmm1, %xmm0, %xmm0
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; CHECK-F16C-NEXT: retq
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define float @test_sitofp_fadd_i32(i32 %a, half* %b) #0 {
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%tmp0 = load half, half* %b
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%tmp1 = sitofp i32 %a to half
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%tmp2 = fadd half %tmp0, %tmp1
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%tmp3 = fpext half %tmp2 to float
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ret float %tmp3
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}
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attributes #0 = { nounwind }
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