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74609b7c8b
Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=i686-pc-windows-msvc18.0.0 -mcpu=pentium4
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define x86_thiscallcc i32* @fn4(i32* %this, i8* dereferenceable(1) %p1) {
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entry:
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%DL = getelementptr inbounds i32, i32* %this, i32 0
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%call.i = tail call x86_thiscallcc i64 @fn1(i32* %DL)
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%getTypeAllocSize___trans_tmp_2.i = getelementptr inbounds i32, i32* %this, i32 0
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%0 = load i32, i32* %getTypeAllocSize___trans_tmp_2.i, align 4
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%call.i8 = tail call x86_thiscallcc i64 @fn1(i32* %DL)
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%1 = insertelement <2 x i64> undef, i64 %call.i, i32 0
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%2 = insertelement <2 x i64> %1, i64 %call.i8, i32 1
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%3 = add nsw <2 x i64> %2, <i64 7, i64 7>
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%4 = sdiv <2 x i64> %3, <i64 8, i64 8>
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%5 = add nsw <2 x i64> %4, <i64 1, i64 1>
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%6 = load i32, i32* %getTypeAllocSize___trans_tmp_2.i, align 4
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%7 = insertelement <2 x i32> undef, i32 %0, i32 0
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%8 = insertelement <2 x i32> %7, i32 %6, i32 1
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%9 = zext <2 x i32> %8 to <2 x i64>
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%10 = srem <2 x i64> %5, %9
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%11 = sub <2 x i64> %5, %10
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%12 = trunc <2 x i64> %11 to <2 x i32>
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%13 = extractelement <2 x i32> %12, i32 0
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%14 = extractelement <2 x i32> %12, i32 1
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%cmp = icmp eq i32 %13, %14
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br i1 %cmp, label %if.then, label %cleanup
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if.then:
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%call4 = tail call x86_thiscallcc i32* @fn3(i8* nonnull %p1)
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br label %cleanup
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cleanup:
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%retval.0 = phi i32* [ %call4, %if.then ], [ undef, %entry ]
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ret i32* %retval.0
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}
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declare x86_thiscallcc i32* @fn3(i8*)
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declare x86_thiscallcc i64 @fn1(i32*)
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