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7e501cf4c3
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
llvm-svn: 186280
103 lines
2.2 KiB
LLVM
103 lines
2.2 KiB
LLVM
; Test 64-bit comparisons in which the second operand is zero-extended
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; from a PC-relative i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i32 1
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@h = global i32 1, align 2, section "foo"
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; Check unsigned comparison.
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define i64 @f1(i64 %src1) {
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; CHECK-LABEL: f1:
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; CHECK: clgfrl %r2, g
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i32 *@g
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%src2 = zext i32 %val to i64
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%cond = icmp ult i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Check signed comparison.
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define i64 @f2(i64 %src1) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: clgfrl
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; CHECK: br %r14
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entry:
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%val = load i32 *@g
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%src2 = zext i32 %val to i64
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%cond = icmp slt i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Check equality.
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define i64 @f3(i64 %src1) {
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; CHECK-LABEL: f3:
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; CHECK: clgfrl %r2, g
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; CHECK-NEXT: je
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; CHECK: br %r14
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entry:
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%val = load i32 *@g
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%src2 = zext i32 %val to i64
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%cond = icmp eq i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Check inequality.
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define i64 @f4(i64 %src1) {
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; CHECK-LABEL: f4:
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; CHECK: clgfrl %r2, g
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; CHECK-NEXT: jlh
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; CHECK: br %r14
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entry:
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%val = load i32 *@g
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%src2 = zext i32 %val to i64
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%cond = icmp ne i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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; Repeat f1 with an unaligned address.
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define i64 @f5(i64 %src1) {
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; CHECK-LABEL: f5:
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; CHECK: larl [[REG:%r[0-5]]], h
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; CHECK: clgf %r2, 0([[REG]])
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i32 *@h, align 2
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%src2 = zext i32 %val to i64
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%cond = icmp ult i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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%res = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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ret i64 %res
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}
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