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dcd7a1bde2
Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 llvm-svn: 243638
22 lines
665 B
LLVM
22 lines
665 B
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@f = global float 0x40147E6B80000000, align 4
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@d_f = common global double 0.000000e+00, align 8
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@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
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; Function Attrs: nounwind
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define void @dv() #0 {
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entry:
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%0 = load float, float* @f, align 4
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%conv = fpext float %0 to double
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; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}}
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store double %conv, double* @d_f, align 8
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ret void
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}
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attributes #1 = { nounwind }
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