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dcd7a1bde2
Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 llvm-svn: 243638
25 lines
654 B
LLVM
25 lines
654 B
LLVM
; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \
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; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s
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; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
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%struct.s = type { [4 x i8], i32 }
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define i32 @main() nounwind uwtable {
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entry:
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%foo = alloca %struct.s, align 4
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%0 = bitcast %struct.s* %foo to i32*
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%bf.load = load i32, i32* %0, align 4
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%bf.lshr = lshr i32 %bf.load, 2
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%cmp = icmp ne i32 %bf.lshr, 2
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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unreachable
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if.end:
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ret i32 0
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}
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; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
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