Matt Arsenault 34dde63750 MIR: Fix missing serialization for HasTailCall		2021-03-21 13:14:04 -04:00
..
AArch64	Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"	2021-03-18 16:01:02 -07:00
AMDGPU	AMDGPU/GlobalISel: Enable CSE in pre-legalizer combiner	2021-03-21 10:07:37 -04:00
ARC
ARM	[DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling	2021-03-19 16:02:31 +00:00
AVR
BPF
Generic	[XCore] Remove XFAIL: xcore from passing test.	2021-03-18 15:46:24 +00:00
Hexagon	[Hexagon] Add support for named registers cs0 and cs1	2021-03-18 09:53:22 -05:00
Inputs
Lanai
M68k	[DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling	2021-03-19 16:02:31 +00:00
Mips
MIR	MIR: Fix missing serialization for HasTailCall	2021-03-21 13:14:04 -04:00
MSP430
NVPTX
PowerPC	[DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling	2021-03-19 16:02:31 +00:00
RISCV	[RISCV] remove redundant instruction when eliminate frame index	2021-03-21 18:54:00 +08:00
SPARC
SystemZ
Thumb	[ARM] Use lrdsb for more thumb1 loads.	2021-03-17 15:29:02 +00:00
Thumb2	[ARM] VINS f16 pattern	2021-03-21 12:00:06 +00:00
VE
WebAssembly	[WebAssembly] Finalize SIMD names and opcodes	2021-03-18 11:21:25 -07:00
WinCFGuard
WinEH
X86	[X86][AVX] ComputeNumSignBitsForTargetNode - add X86ISD::VBROADCAST handling for scalar sources	2021-03-21 12:22:51 +00:00
XCore