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3ed152b528
TargetIRAnalysis access path directly rather than implementing getTTI. This even removes getTTI from the interface. It's more efficient for each target to just register a precise callback that creates their specific TTI. As part of this, all of the targets which are building their subtargets individually per-function now build their TTI instance with the function and thus look up the correct subtarget and cache it. NVPTX, R600, and XCore currently don't leverage this functionality, but its trivial for them to add it now. llvm-svn: 227735
80 lines
2.5 KiB
C++
80 lines
2.5 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
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#define LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUIntrinsicInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "R600ISelLowering.h"
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#include "llvm/IR/DataLayout.h"
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namespace llvm {
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//===----------------------------------------------------------------------===//
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// AMDGPU Target Machine (R600+)
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//===----------------------------------------------------------------------===//
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class AMDGPUTargetMachine : public LLVMTargetMachine {
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private:
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const DataLayout DL;
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protected:
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TargetLoweringObjectFile *TLOF;
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AMDGPUSubtarget Subtarget;
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AMDGPUIntrinsicInfo IntrinsicInfo;
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public:
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AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
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StringRef CPU, TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL);
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~AMDGPUTargetMachine();
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// FIXME: This is currently broken, the DataLayout needs to move to
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// the target machine.
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const DataLayout *getDataLayout() const override {
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return &DL;
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}
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const AMDGPUSubtarget *getSubtargetImpl() const override {
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return &Subtarget;
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}
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const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
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return &IntrinsicInfo;
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}
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetIRAnalysis getTargetIRAnalysis() override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF;
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}
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};
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//===----------------------------------------------------------------------===//
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// GCN Target Machine (SI+)
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//===----------------------------------------------------------------------===//
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class GCNTargetMachine : public AMDGPUTargetMachine {
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public:
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GCNTargetMachine(const Target &T, StringRef TT, StringRef FS,
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StringRef CPU, TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL);
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};
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} // End namespace llvm
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#endif
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