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https://github.com/RPCS3/llvm-mirror.git
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a1b187e1bf
This patch teaches FastIsel the following two things: 1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types; 2) On AVX, no instructions are needed for bitcasts between 256-bit vector types. Example: %1 = bitcast <4 x i31> %V to <2 x i64> Before (-fast-isel -fast-isel-abort=1): FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64> Now we don't fall back to SelectionDAG and we correctly fold that computation propagating the register associated to %V. Originally reviewed here: http://reviews.llvm.org/D13347 llvm-svn: 249147
246 lines
5.9 KiB
LLVM
246 lines
5.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -fast-isel -fast-isel-abort=1 -asm-verbose=0 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel -fast-isel-abort=1 -asm-verbose=0 | FileCheck %s
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;
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; Bitcasts between 128-bit vector types are no-ops since no instruction is
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; needed for the conversion.
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define <2 x i64> @v4i32_to_v2i64(<4 x i32> %a) {
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;CHECK-LABEL: v4i32_to_v2i64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x i32> %a to <2 x i64>
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ret <2 x i64> %1
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}
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define <2 x i64> @v8i16_to_v2i64(<8 x i16> %a) {
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;CHECK-LABEL: v8i16_to_v2i64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <8 x i16> %a to <2 x i64>
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ret <2 x i64> %1
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}
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define <2 x i64> @v16i8_to_v2i64(<16 x i8> %a) {
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;CHECK-LABEL: v16i8_to_v2i64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <16 x i8> %a to <2 x i64>
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ret <2 x i64> %1
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}
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define <2 x i64> @v2f64_to_v2i64(<2 x double> %a) {
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;CHECK-LABEL: v2f64_to_v2i64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x double> %a to <2 x i64>
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ret <2 x i64> %1
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}
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define <2 x i64> @v4f32_to_v2i64(<4 x float> %a) {
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;CHECK-LABEL: v4f32_to_v2i64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x float> %a to <2 x i64>
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ret <2 x i64> %1
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}
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define <4 x i32> @v2i64_to_v4i32(<2 x i64> %a) {
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;CHECK-LABEL: v2i64_to_v4i32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x i64> %a to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @v8i16_to_v4i32(<8 x i16> %a) {
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;CHECK-LABEL: v8i16_to_v4i32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <8 x i16> %a to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @v16i8_to_v4i32(<16 x i8> %a) {
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;CHECK-LABEL: v16i8_to_v4i32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <16 x i8> %a to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @v2f64_to_v4i32(<2 x double> %a) {
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;CHECK-LABEL: v2f64_to_v4i32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x double> %a to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @v4f32_to_v4i32(<4 x float> %a) {
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;CHECK-LABEL: v4f32_to_v4i32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x float> %a to <4 x i32>
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ret <4 x i32> %1
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}
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define <8 x i16> @v2i64_to_v8i16(<2 x i64> %a) {
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;CHECK-LABEL: v2i64_to_v8i16:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x i64> %a to <8 x i16>
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ret <8 x i16> %1
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}
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define <8 x i16> @v4i32_to_v8i16(<4 x i32> %a) {
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;CHECK-LABEL: v4i32_to_v8i16:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x i32> %a to <8 x i16>
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ret <8 x i16> %1
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}
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define <8 x i16> @v16i8_to_v8i16(<16 x i8> %a) {
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;CHECK-LABEL: v16i8_to_v8i16:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <16 x i8> %a to <8 x i16>
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ret <8 x i16> %1
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}
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define <8 x i16> @v2f64_to_v8i16(<2 x double> %a) {
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;CHECK-LABEL: v2f64_to_v8i16:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x double> %a to <8 x i16>
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ret <8 x i16> %1
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}
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define <8 x i16> @v4f32_to_v8i16(<4 x float> %a) {
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;CHECK-LABEL: v4f32_to_v8i16:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x float> %a to <8 x i16>
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ret <8 x i16> %1
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}
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define <16 x i8> @v8i16_to_v16i8(<8 x i16> %a) {
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;CHECK-LABEL: v8i16_to_v16i8:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <8 x i16> %a to <16 x i8>
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ret <16 x i8> %1
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}
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define <16 x i8> @v2i64_to_v16i8(<2 x i64> %a) {
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;CHECK-LABEL: v2i64_to_v16i8:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x i64> %a to <16 x i8>
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ret <16 x i8> %1
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}
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define <16 x i8> @v4i32_to_v16i8(<4 x i32> %a) {
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;CHECK-LABEL: v4i32_to_v16i8:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x i32> %a to <16 x i8>
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ret <16 x i8> %1
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}
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define <16 x i8> @v2f64_to_v16i8(<2 x double> %a) {
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;CHECK-LABEL: v2f64_to_v16i8:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x double> %a to <16 x i8>
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ret <16 x i8> %1
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}
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define <16 x i8> @v4f32_to_v16i8(<4 x float> %a) {
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;CHECK-LABEL: v4f32_to_v16i8:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x float> %a to <16 x i8>
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ret <16 x i8> %1
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}
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define <4 x float> @v16i8_to_v4f32(<16 x i8> %a) {
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;CHECK-LABEL: v16i8_to_v4f32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <16 x i8> %a to <4 x float>
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ret <4 x float> %1
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}
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define <4 x float> @v8i16_to_v4f32(<8 x i16> %a) {
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;CHECK-LABEL: v8i16_to_v4f32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <8 x i16> %a to <4 x float>
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ret <4 x float> %1
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}
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define <4 x float> @v2i64_to_v4f32(<2 x i64> %a) {
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;CHECK-LABEL: v2i64_to_v4f32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x i64> %a to <4 x float>
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ret <4 x float> %1
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}
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define <4 x float> @v4i32_to_v4f32(<4 x i32> %a) {
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;CHECK-LABEL: v4i32_to_v4f32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x i32> %a to <4 x float>
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ret <4 x float> %1
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}
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define <4 x float> @v2f64_to_v4f32(<2 x double> %a) {
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;CHECK-LABEL: v2f64_to_v4f32:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x double> %a to <4 x float>
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ret <4 x float> %1
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}
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define <2 x double> @v4f32_to_v2f64(<4 x float> %a) {
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;CHECK-LABEL: v4f32_to_v2f64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x float> %a to <2 x double>
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ret <2 x double> %1
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}
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define <2 x double> @v16i8_to_v2f64(<16 x i8> %a) {
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;CHECK-LABEL: v16i8_to_v2f64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <16 x i8> %a to <2 x double>
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ret <2 x double> %1
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}
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define <2 x double> @v8i16_to_v2f64(<8 x i16> %a) {
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;CHECK-LABEL: v8i16_to_v2f64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <8 x i16> %a to <2 x double>
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ret <2 x double> %1
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}
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define <2 x double> @v2i64_to_v2f64(<2 x i64> %a) {
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;CHECK-LABEL: v2i64_to_v2f64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <2 x i64> %a to <2 x double>
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ret <2 x double> %1
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}
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define <2 x double> @v4i32_to_v2f64(<4 x i32> %a) {
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;CHECK-LABEL: v4i32_to_v2f64:
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;CHECK-NEXT: .cfi_startproc
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;CHECK-NEXT: ret
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%1 = bitcast <4 x i32> %a to <2 x double>
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ret <2 x double> %1
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}
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