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Recommited, after some fixing with test cases. Updated test cases: test/CodeGen/AArch64/arm64-misched-memdep-bug.ll test/CodeGen/AArch64/tailcall_misched_graph.ll Temporarily disabled test cases: test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll test/CodeGen/PowerPC/ppc64-fastcc.ll (partially updated) test/CodeGen/PowerPC/vsx-fma-m.ll test/CodeGen/PowerPC/vsx-fma-sp.ll http://reviews.llvm.org/D8705 Reviewers: Hal Finkel, Andy Trick. llvm-svn: 259673
26 lines
1.1 KiB
LLVM
26 lines
1.1 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; Test for bug in misched memory dependency calculation.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: misched_bug:BB#0 entry
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; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
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; CHECK: Successors:
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; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2
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; CHECK-NEXT: ch SU(4): Latency=0
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; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
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; CHECK: Successors:
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; CHECK: ch SU(4): Latency=0
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; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
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; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2
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; CHECK: ** ScheduleDAGMI::schedule picking next node
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define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
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entry:
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%ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1
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%val1 = load i32, i32* %ptr1_plus1, align 4
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store i32 0, i32* %ptr1, align 4
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store i32 0, i32* %ptr2, align 4
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ret i32 %val1
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}
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