Simon Pilgrim 0e90564849 [AMDGPU] Regenerate extractelt->truncate test. ...

Prep work for D60462

llvm-svn: 358746

2019-04-19 09:49:04 +00:00

..

AArch64

[AArch64] add tests for mul-by-element; NFC

2019-04-18 21:48:46 +00:00

AMDGPU

[AMDGPU] Regenerate extractelt->truncate test.

2019-04-19 09:49:04 +00:00

ARC

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ARM

[AsmPrinter] defer %c to base class for ARM, PPC, and Hexagon. NFC

2019-04-17 18:22:48 +00:00

AVR

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BPF

[BPF] add proper multi-dimensional array support

2019-03-28 21:59:49 +00:00

Generic

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Hexagon

[AsmPrinter] defer %c to base class for ARM, PPC, and Hexagon. NFC

2019-04-17 18:22:48 +00:00

Inputs

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Lanai

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Mips

[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.

2019-04-15 05:04:20 +00:00

MIR

[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

2019-04-05 19:28:09 +00:00

MSP430

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NVPTX

[NVPTX] Fix the codegen for llvm.round.

2019-04-01 16:10:26 +00:00

PowerPC

[PowerPC] Fix wrong ElemSIze when calling isConsecutiveLS()

2019-04-18 07:24:15 +00:00

RISCV

[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS

2019-04-16 14:38:32 +00:00

SPARC

[Sparc] Fix incorrect MI insertion position for spilling f128.

2019-04-10 01:56:32 +00:00

SystemZ

Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg

2019-04-10 18:00:41 +00:00

Thumb

[ARM] Add an extra constant hoisting test. NFC

2019-04-10 18:05:57 +00:00

Thumb2

[ARM] Add an extra test for constant hoist. NFC

2019-04-10 19:18:58 +00:00

WebAssembly

[WebAssembly] Add mutable-globals to bleeding-edge CPU

2019-04-12 20:39:53 +00:00

WinCFGuard

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WinEH

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X86

[X86] Turn (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) if the AND could match a movzx.

2019-04-19 05:48:13 +00:00

XCore

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