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05a99347e9
Reapply r242500 now that the swift schedmodel includes LDRLIT. This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 llvm-svn: 242588
117 lines
4.0 KiB
LLVM
117 lines
4.0 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT
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; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
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; dependency) when it isn't dependent on last CPSR defining instruction.
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; rdar://8928208
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
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entry:
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; CHECK-LABEL: t1:
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; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2
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; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
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; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0
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; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r3
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; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
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%0 = mul nsw i32 %a, %b
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%1 = mul nsw i32 %c, %d
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%2 = mul nsw i32 %0, %1
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ret i32 %2
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}
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; Avoid partial CPSR dependency via loop backedge.
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; rdar://10357570
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define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
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entry:
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; CHECK-LABEL: t2:
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br label %while.body
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while.body:
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; CHECK: while.body
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; CHECK: mul r{{[0-9]+}}
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; CHECK-NOT: muls
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%ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
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%ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
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%0 = load i32, i32* %ptr1.addr.09, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
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%1 = load i32, i32* %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
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%2 = load i32, i32* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
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%3 = load i32, i32* %arrayidx4, align 4
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%add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
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%mul = mul i32 %1, %0
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%mul5 = mul i32 %mul, %2
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%mul6 = mul i32 %mul5, %3
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store i32 %mul6, i32* %ptr2.addr.08, align 4
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%incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
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%tobool = icmp eq i32* %incdec.ptr, null
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br i1 %tobool, label %while.end, label %while.body
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while.end:
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ret void
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}
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; Allow partial CPSR dependency when code size is the priority.
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; rdar://12878928
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define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
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entry:
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; CHECK-LABEL: t3:
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br label %while.body
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while.body:
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; CHECK: while.body
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; CHECK: mul r{{[0-9]+}}
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; CHECK: muls
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%ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
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%ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
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%0 = load i32, i32* %ptr1.addr.09, align 4
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%arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
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%1 = load i32, i32* %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
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%2 = load i32, i32* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
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%3 = load i32, i32* %arrayidx4, align 4
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%add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
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%mul = mul i32 %1, %0
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%mul5 = mul i32 %mul, %2
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%mul6 = mul i32 %mul5, %3
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store i32 %mul6, i32* %ptr2.addr.08, align 4
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%incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
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%tobool = icmp eq i32* %incdec.ptr, null
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br i1 %tobool, label %while.end, label %while.body
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while.end:
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ret void
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}
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; Avoid producing tMOVi8 after a high-latency flag-setting operation.
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; <rdar://problem/13468102>
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define void @t4(i32* nocapture %p, double* nocapture %q) {
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entry:
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; CHECK: t4
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; CHECK: vmrs APSR_nzcv, fpscr
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; CHECK: if.then
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; CHECK-NOT: movs
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%0 = load double, double* %q, align 4
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%cmp = fcmp olt double %0, 1.000000e+01
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%incdec.ptr1 = getelementptr inbounds i32, i32* %p, i32 1
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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store i32 7, i32* %p, align 4
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%incdec.ptr2 = getelementptr inbounds i32, i32* %p, i32 2
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store i32 8, i32* %incdec.ptr1, align 4
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store i32 9, i32* %incdec.ptr2, align 4
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br label %if.end
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if.else:
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store i32 3, i32* %p, align 4
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%incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 2
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store i32 5, i32* %incdec.ptr1, align 4
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store i32 6, i32* %incdec.ptr5, align 4
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br label %if.end
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if.end:
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ret void
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}
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