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099f4c5254
Allow a target to do something other than search for copies that will avoid cross register bank copies. Implement for SI by only rewriting the most basic copies, so it should look through anything like a subregister extract. I'm not entirely satisified with this because it seems like eliminating a reg_sequence that isn't fully used should work generically for all targets without them having to override something. However, it seems to be tricky to have a simple implementation of this without rewriting to invalid kinds of subregister copies on some targets. I'm not sure if there is currently a generic way to easily check if a subregister index would be valid for the current use. The current set of TargetRegisterInfo::get*Class functions don't quite behave like I would expect (e.g. getSubClassWithSubReg returns the maximal register class rather than the minimal), so I'm not sure how to make the generic test keep searching if SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making the default implementation to check for simple copies breaks a variety of ARM and x86 tests by producing illegal subregister uses. The ARM tests are not actually changed since it should still be using the same sharesSameRegisterFile implementation, this just relaxes them to not check for specific registers. llvm-svn: 248478
108 lines
3.6 KiB
LLVM
108 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
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; RUN: llc -mtriple=armeb-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
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define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vcombine8
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; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
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; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
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; CHECK-LE-DAG: vmov r0, r1, [[LD0]]
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; CHECK-LE-DAG: vmov r2, r3, [[LD1]]
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; CHECK-BE-DAG: vmov r1, r0, d16
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; CHECK-BE-DAG: vmov r3, r2, d17
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vcombine16
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; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
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; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
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; CHECK-LE-DAG: vmov r0, r1, [[LD0]]
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; CHECK-LE-DAG: vmov r2, r3, [[LD1]]
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; CHECK-BE-DAG: vmov r1, r0, d16
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; CHECK-BE-DAG: vmov r3, r2, d17
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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; CHECK-LABEL: vcombine32
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; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
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; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
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; CHECK-LE: vmov r0, r1, [[LD0]]
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; CHECK-LE: vmov r2, r3, [[LD1]]
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; CHECK-BE: vmov r1, r0, d16
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; CHECK-BE: vmov r3, r2, d17
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = load <2 x i32>, <2 x i32>* %B
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%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %tmp3
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}
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define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
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; CHECK-LABEL: vcombinefloat
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; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
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; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
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; CHECK-LE: vmov r0, r1, [[LD0]]
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; CHECK-LE: vmov r2, r3, [[LD1]]
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; CHECK-BE: vmov r1, r0, d16
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; CHECK-BE: vmov r3, r2, d17
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x float> %tmp3
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}
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define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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; CHECK-LABEL: vcombine64
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; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
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; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
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; CHECK-LE: vmov r0, r1, [[LD0]]
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; CHECK-LE: vmov r2, r3, [[LD1]]
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; CHECK-BE: vmov r1, r0, [[LD0]]
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; CHECK-BE: vmov r3, r2, [[LD1]]
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%tmp1 = load <1 x i64>, <1 x i64>* %A
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%tmp2 = load <1 x i64>, <1 x i64>* %B
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%tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1>
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ret <2 x i64> %tmp3
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}
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; Check for vget_low and vget_high implemented with shufflevector. PR8411.
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; They should not require storing to the stack.
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define <4 x i16> @vget_low16(<8 x i16>* %A) nounwind {
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; CHECK: vget_low16
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; CHECK-NOT: vst
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; CHECK-LE: vmov r0, r1, d16
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; CHECK-BE: vmov r1, r0, d16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %tmp2
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}
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define <8 x i8> @vget_high8(<16 x i8>* %A) nounwind {
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; CHECK: vget_high8
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; CHECK-NOT: vst
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; CHECK-LE: vmov r0, r1, d17
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; CHECK-BE: vmov r1, r0, d16
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%tmp1 = load <16 x i8>, <16 x i8>* %A
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %tmp2
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}
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