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The virtual register containing the address for returned value on stack should in the DAG be represented with a CopyFromReg node and not a Register node. Otherwise, InstrEmitter will not make sure that it ends up in the right register class for the target instruction. SystemZ needs this, becuause the reg class for address registers is a subset of the general 64 bit register class. test/SystemZ/CodeGen/args-07.ll and args-04.ll updated to run with -verify-machineinstrs. Reviewed by Hal Finkel. llvm-svn: 253461
61 lines
1.8 KiB
LLVM
61 lines
1.8 KiB
LLVM
; Test multiple return values (LLVM ABI extension)
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -verify-machineinstrs| FileCheck %s
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; Up to four integer return values fit into GPRs.
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define { i64, i64, i64, i64 } @f1() {
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; CHECK-LABEL: f1:
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; CHECK: lghi %r2, 0
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; CHECK: lghi %r3, 1
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; CHECK: lghi %r4, 2
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; CHECK: lghi %r5, 3
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; CHECK: br %r14
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ret { i64, i64, i64, i64 } { i64 0, i64 1, i64 2, i64 3 }
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}
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; More than four integer return values use sret.
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define { i64, i64, i64, i64, i64 } @f2() {
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; CHECK-LABEL: f2:
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; CHECK: mvghi 32(%r2), 4
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; CHECK: mvghi 24(%r2), 3
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; CHECK: mvghi 16(%r2), 2
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; CHECK: mvghi 8(%r2), 1
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; CHECK: mvghi 0(%r2), 0
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; CHECK: br %r14
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ret { i64, i64, i64, i64, i64 } { i64 0, i64 1, i64 2, i64 3, i64 4 }
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}
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; Up to four floating-point return values fit into FPRs.
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define { double, double, double, double } @f3() {
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; CHECK-LABEL: f3:
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; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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; CHECK: ldeb %f0, 0([[TMP]])
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; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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; CHECK: ldeb %f2, 0([[TMP]])
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; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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; CHECK: ldeb %f4, 0([[TMP]])
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; CHECK: larl [[TMP:%r[0-5]]], .LCPI
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; CHECK: ldeb %f6, 0([[TMP]])
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; CHECK: br %r14
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ret { double, double, double, double }
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{ double 1.0, double 2.0, double 3.0, double 4.0 }
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}
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; More than four floating-point return values use sret.
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define { double, double, double, double, double } @f4() {
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; CHECK-LABEL: f4:
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; CHECK: llihh [[TMP:%r[0-5]]], 16404
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; CHECK: stg [[TMP]], 32(%r2)
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; CHECK: llihh [[TMP:%r[0-5]]], 16400
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; CHECK: stg [[TMP]], 24(%r2)
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; CHECK: llihh [[TMP:%r[0-5]]], 16392
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; CHECK: stg [[TMP]], 16(%r2)
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; CHECK: llihh [[TMP:%r[0-5]]], 16384
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; CHECK: stg [[TMP]], 8(%r2)
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; CHECK: llihh [[TMP:%r[0-5]]], 16368
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; CHECK: stg [[TMP]], 0(%r2)
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; CHECK: br %r14
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ret { double, double, double, double, double }
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{ double 1.0, double 2.0, double 3.0, double 4.0, double 5.0 }
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}
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