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80d5f68422
Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
140 lines
3.1 KiB
LLVM
140 lines
3.1 KiB
LLVM
; Test memcmp using CLC, with i64 results.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @memcmp(i8 *%src1, i8 *%src2, i64 %size)
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; Zero-length comparisons should be optimized away.
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define i64 @f1(i8 *%src1, i8 *%src2) {
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; CHECK-LABEL: f1:
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; CHECK: lghi %r2, 0
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; CHECK: br %r14
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 0)
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ret i64 %res
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}
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; Check a case where the result is used as an integer.
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define i64 @f2(i8 *%src1, i8 *%src2) {
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; CHECK-LABEL: f2:
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; CHECK: clc 0(2,%r2), 0(%r3)
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: rll [[REG]], [[REG]], 31
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; CHECK: lgfr %r2, [[REG]]
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; CHECK: br %r14
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 2)
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ret i64 %res
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}
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; Check a case where the result is tested for equality.
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define void @f3(i8 *%src1, i8 *%src2, i64 *%dest) {
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; CHECK-LABEL: f3:
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; CHECK: clc 0(3,%r2), 0(%r3)
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; CHECK-NEXT: ber %r14
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; CHECK: br %r14
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 3)
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%cmp = icmp eq i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 0, i64 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check a case where the result is tested for inequality.
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define void @f4(i8 *%src1, i8 *%src2, i64 *%dest) {
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; CHECK-LABEL: f4:
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; CHECK: clc 0(4,%r2), 0(%r3)
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; CHECK-NEXT: blhr %r14
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; CHECK: br %r14
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entry:
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 4)
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%cmp = icmp ne i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 0, i64 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check a case where the result is tested via slt.
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define void @f5(i8 *%src1, i8 *%src2, i64 *%dest) {
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; CHECK-LABEL: f5:
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; CHECK: clc 0(5,%r2), 0(%r3)
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; CHECK-NEXT: blr %r14
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; CHECK: br %r14
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entry:
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 5)
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%cmp = icmp slt i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 0, i64 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check a case where the result is tested for sgt.
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define void @f6(i8 *%src1, i8 *%src2, i64 *%dest) {
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; CHECK-LABEL: f6:
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; CHECK: clc 0(6,%r2), 0(%r3)
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; CHECK-NEXT: bhr %r14
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; CHECK: br %r14
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entry:
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 6)
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%cmp = icmp sgt i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 0, i64 *%dest
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br label %exit
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exit:
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ret void
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}
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; Check the upper end of the CLC range. Here the result is used both as
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; an integer and for branching.
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define i64 @f7(i8 *%src1, i8 *%src2, i64 *%dest) {
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; CHECK-LABEL: f7:
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; CHECK: clc 0(256,%r2), 0(%r3)
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: rll [[REG]], [[REG]], 31
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; CHECK: lgfr %r2, [[REG]]
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; CHECK: blr %r14
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; CHECK: br %r14
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entry:
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 256)
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%cmp = icmp slt i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 0, i64 *%dest
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br label %exit
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exit:
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ret i64 %res
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}
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; 257 bytes needs two CLCs.
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define i64 @f8(i8 *%src1, i8 *%src2) {
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; CHECK-LABEL: f8:
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; CHECK: clc 0(256,%r2), 0(%r3)
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; CHECK: jlh [[LABEL:\..*]]
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; CHECK: clc 256(1,%r2), 256(%r3)
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; CHECK: [[LABEL]]:
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: br %r14
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%res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 257)
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ret i64 %res
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}
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