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f8020709f1
We're going to stop generating PSIGN, so calling a test "psign" isn't ideal. Instead, call these tests what they really are: variable blends using logic. Also add a test to exhibit a case we're currently missing in the PSIGN combine. llvm-svn: 261022
67 lines
1.9 KiB
LLVM
67 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; CHECK: vpandn
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; CHECK: vpandn %ymm
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; CHECK: ret
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define <4 x i64> @vpandn(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%y = xor <4 x i64> %a2, <i64 -1, i64 -1, i64 -1, i64 -1>
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%x = and <4 x i64> %a, %y
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ret <4 x i64> %x
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}
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; CHECK: vpand
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; CHECK: vpand %ymm
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; CHECK: ret
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define <4 x i64> @vpand(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = and <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK: vpor
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; CHECK: vpor %ymm
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; CHECK: ret
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define <4 x i64> @vpor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = or <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK: vpxor
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; CHECK: vpxor %ymm
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; CHECK: ret
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define <4 x i64> @vpxor(<4 x i64> %a, <4 x i64> %b) nounwind uwtable readnone ssp {
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entry:
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; Force the execution domain with an add.
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%a2 = add <4 x i64> %a, <i64 1, i64 1, i64 1, i64 1>
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%x = xor <4 x i64> %a2, %b
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ret <4 x i64> %x
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}
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; CHECK: vpblendvb
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; CHECK: vpblendvb %ymm
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; CHECK: ret
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define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) {
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%min = select <32 x i1> %cond, <32 x i8> %x, <32 x i8> %y
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ret <32 x i8> %min
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}
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define <8 x i32> @allOnes() nounwind {
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; CHECK: vpcmpeqd
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; CHECK-NOT: vinsert
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ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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}
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define <16 x i16> @allOnes2() nounwind {
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; CHECK: vpcmpeqd
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; CHECK-NOT: vinsert
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ret <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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}
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