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6b7c9ae783
The old implementation assumed LP64 which is broken for x32. Specifically, the MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit physreg copy instruction' error message to be reported. This patch also enable the h-register*ll tests for x32. Differential Revision: http://reviews.llvm.org/D12336 Patch by João Porto llvm-svn: 247058
108 lines
2.4 KiB
LLVM
108 lines
2.4 KiB
LLVM
; RUN: llc < %s -mattr=-bmi -mtriple=x86_64-linux | FileCheck %s -check-prefix=X86-64
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; RUN: llc < %s -mattr=-bmi -mtriple=x86_64-linux-gnux32 | FileCheck %s -check-prefix=X86-64
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; RUN: llc < %s -mattr=-bmi -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64
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; RUN: llc < %s -mattr=-bmi -march=x86 | FileCheck %s -check-prefix=X86-32
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; Use h registers. On x86-64, codegen doesn't support general allocation
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; of h registers yet, due to x86 encoding complications.
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define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
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; X86-64-LABEL: bar64:
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; X86-64: shrq $8, %rdi
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; X86-64: incb %dil
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; See FIXME: on regclass GR8.
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; It could be optimally transformed like; incb %ch; movb %ch, (%rdx)
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; WIN64-LABEL: bar64:
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; WIN64: shrq $8, %rcx
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; WIN64: incb %cl
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; X86-32-LABEL: bar64:
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; X86-32: incb %ah
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%t0 = lshr i64 %x, 8
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%t1 = trunc i64 %t0 to i8
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%t2 = add i8 %t1, 1
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store i8 %t2, i8* %p
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ret void
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}
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define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
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; X86-64-LABEL: bar32:
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; X86-64: shrl $8, %edi
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; X86-64: incb %dil
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; WIN64-LABEL: bar32:
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; WIN64: shrl $8, %ecx
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; WIN64: incb %cl
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; X86-32-LABEL: bar32:
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; X86-32: incb %ah
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%t0 = lshr i32 %x, 8
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%t1 = trunc i32 %t0 to i8
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%t2 = add i8 %t1, 1
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store i8 %t2, i8* %p
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ret void
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}
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define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
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; X86-64-LABEL: bar16:
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; X86-64: shrl $8, %edi
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; X86-64: incb %dil
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; WIN64-LABEL: bar16:
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; WIN64: shrl $8, %ecx
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; WIN64: incb %cl
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; X86-32-LABEL: bar16:
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; X86-32: incb %ah
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%t0 = lshr i16 %x, 8
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%t1 = trunc i16 %t0 to i8
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%t2 = add i8 %t1, 1
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store i8 %t2, i8* %p
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ret void
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}
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define i64 @qux64(i64 inreg %x) nounwind {
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; X86-64-LABEL: qux64:
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; X86-64: movq %rdi, %rax
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; X86-64: movzbl %ah, %eax
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; WIN64-LABEL: qux64:
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; WIN64: movzbl %ch, %eax
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; X86-32-LABEL: qux64:
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; X86-32: movzbl %ah, %eax
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%t0 = lshr i64 %x, 8
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%t1 = and i64 %t0, 255
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ret i64 %t1
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}
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define i32 @qux32(i32 inreg %x) nounwind {
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; X86-64-LABEL: qux32:
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; X86-64: movl %edi, %eax
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; X86-64: movzbl %ah, %eax
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; WIN64-LABEL: qux32:
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; WIN64: movzbl %ch, %eax
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; X86-32-LABEL: qux32:
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; X86-32: movzbl %ah, %eax
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%t0 = lshr i32 %x, 8
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%t1 = and i32 %t0, 255
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ret i32 %t1
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}
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define i16 @qux16(i16 inreg %x) nounwind {
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; X86-64-LABEL: qux16:
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; X86-64: movl %edi, %eax
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; X86-64: movzbl %ah, %eax
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; WIN64-LABEL: qux16:
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; WIN64: movzbl %ch, %eax
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; X86-32-LABEL: qux16:
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; X86-32: movzbl %ah, %eax
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%t0 = lshr i16 %x, 8
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ret i16 %t0
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}
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