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This folds (ashr (shl a, [56,48,32,24,16]), SarConst) into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or into (lshr, (sext (a), SarConst - [56,48,32,24,16])) depending on sign of (SarConst - [56,48,32,24,16]) sexts in X86 are MOVs. The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size). However the MOVs have 2 advantages to SHIFTs on x86: 1. MOVs can write to a register that differs from source. 2. MOVs accept memory operands. This fixes PR24373. Patch by: evgeny.v.stupachenko@intel.com Differential Revision: http://reviews.llvm.org/D13161 llvm-svn: 255761
44 lines
951 B
LLVM
44 lines
951 B
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define i32 @shl48sar47(i64 %a) #0 {
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; CHECK-LABEL: shl48sar47:
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; CHECK: # BB#0:
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; CHECK-NEXT: movswq %di, %rax
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%1 = shl i64 %a, 48
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%2 = ashr exact i64 %1, 47
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i32 @shl48sar49(i64 %a) #0 {
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; CHECK-LABEL: shl48sar49:
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; CHECK: # BB#0:
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; CHECK-NEXT: movswq %di, %rax
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%1 = shl i64 %a, 48
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%2 = ashr exact i64 %1, 49
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i32 @shl56sar55(i64 %a) #0 {
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; CHECK-LABEL: shl56sar55:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsbq %dil, %rax
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%1 = shl i64 %a, 56
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%2 = ashr exact i64 %1, 55
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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define i32 @shl56sar57(i64 %a) #0 {
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; CHECK-LABEL: shl56sar57:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsbq %dil, %rax
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%1 = shl i64 %a, 56
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%2 = ashr exact i64 %1, 57
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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attributes #0 = { nounwind }
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