1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
llvm-mirror/test/CodeGen/X86/x32-indirectbr.ll
JF Bastien 3ff38c2bd2 x32. Fixes jmp %reg in x32
x32 has 32-bit pointers; x86-64 can't jmp %r32. This patch addresses this issue by explicitly zero-extending brind's target to 64-bits.

Author: jpp

Reviewers: jfb, dschuff, pavel.v.chupin

Subscribers: llvm-commits

Differential revision: http://reviews.llvm.org/D12112

llvm-svn: 245452
2015-08-19 16:17:08 +00:00

27 lines
949 B
LLVM

; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic -fast-isel | FileCheck %s
; Bug 22859
;
; x32 pointers are 32-bits wide. x86-64 indirect branches use the full 64-bit
; registers. Therefore, x32 CodeGen needs to zero extend indirectbr's target to
; 64-bit.
define i8 @test1() nounwind ssp {
entry:
%0 = select i1 undef, ; <i8*> [#uses=1]
i8* blockaddress(@test1, %bb),
i8* blockaddress(@test1, %bb6)
indirectbr i8* %0, [label %bb, label %bb6]
bb: ; preds = %entry
ret i8 1
bb6: ; preds = %entry
ret i8 2
}
; CHECK-LABEL: @test1
; We are looking for a movl ???, %r32 followed by a 64-bit jmp through the
; same register.
; CHECK: movl {{.*}}, %{{e|r}}[[REG:.[^d]*]]{{d?}}
; CHECK-NEXT: jmpq *%r[[REG]]