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483 lines
16 KiB
C++
483 lines
16 KiB
C++
//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb2InstrInfo.h"
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#include "ARM.h"
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#include "ARMConstantPoolValue.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/ADT/SmallVector.h"
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#include "Thumb2InstrInfo.h"
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using namespace llvm;
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Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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// FIXME
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return 0;
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}
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bool
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Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == ARM::GPRRegisterClass &&
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SrcRC == ARM::GPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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} else if (DestRC == ARM::GPRRegisterClass &&
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SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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} else if (DestRC == ARM::tGPRRegisterClass &&
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SrcRC == ARM::GPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
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return true;
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}
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// Handle SPR, DPR, and QPR copies.
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return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
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}
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void Thumb2InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == ARM::GPRRegisterClass) {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
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MachineMemOperand::MOStore, 0,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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return;
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}
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ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
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}
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void Thumb2InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == ARM::GPRRegisterClass) {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
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MachineMemOperand::MOLoad, 0,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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return;
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}
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ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
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}
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void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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unsigned DestReg, unsigned BaseReg, int NumBytes,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const ARMBaseInstrInfo &TII) {
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bool isSub = NumBytes < 0;
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if (isSub) NumBytes = -NumBytes;
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// If profitable, use a movw or movt to materialize the offset.
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// FIXME: Use the scavenger to grab a scratch register.
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if (DestReg != ARM::SP && DestReg != BaseReg &&
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NumBytes >= 4096 &&
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ARM_AM::getT2SOImmVal(NumBytes) == -1) {
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bool Fits = false;
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if (NumBytes < 65536) {
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// Use a movw to materialize the 16-bit constant.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
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.addImm(NumBytes)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
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Fits = true;
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} else if ((NumBytes & 0xffff) == 0) {
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// Use a movt to materialize the 32-bit constant.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
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.addReg(DestReg)
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.addImm(NumBytes >> 16)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
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Fits = true;
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}
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if (Fits) {
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if (isSub) {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
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.addReg(BaseReg, RegState::Kill)
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.addReg(DestReg, RegState::Kill)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
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} else {
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BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
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.addReg(DestReg, RegState::Kill)
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.addReg(BaseReg, RegState::Kill)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
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}
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return;
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}
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}
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while (NumBytes) {
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unsigned ThisVal = NumBytes;
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unsigned Opc = 0;
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if (DestReg == ARM::SP && BaseReg != ARM::SP) {
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// mov sp, rn. Note t2MOVr cannot be used.
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BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
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BaseReg = ARM::SP;
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continue;
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}
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if (BaseReg == ARM::SP) {
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// sub sp, sp, #imm7
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if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
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assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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// FIXME: Fix Thumb1 immediate encoding.
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BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
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.addReg(BaseReg).addImm(ThisVal/4);
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NumBytes = 0;
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continue;
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}
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// sub rd, sp, so_imm
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Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
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if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
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NumBytes = 0;
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} else {
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// FIXME: Move this to ARMAddressingModes.h?
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unsigned RotAmt = CountLeadingZeros_32(ThisVal);
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ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
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NumBytes &= ~ThisVal;
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assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
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"Bit extraction didn't work?");
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}
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} else {
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assert(DestReg != ARM::SP && BaseReg != ARM::SP);
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Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
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if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
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NumBytes = 0;
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} else if (ThisVal < 4096) {
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Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
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NumBytes = 0;
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} else {
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// FIXME: Move this to ARMAddressingModes.h?
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unsigned RotAmt = CountLeadingZeros_32(ThisVal);
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ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
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NumBytes &= ~ThisVal;
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assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
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"Bit extraction didn't work?");
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}
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}
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// Build the new ADD / SUB.
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
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.addReg(BaseReg, RegState::Kill)
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.addImm(ThisVal)));
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BaseReg = DestReg;
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}
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}
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static unsigned
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negativeOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRi12: return ARM::t2LDRi8;
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case ARM::t2LDRHi12: return ARM::t2LDRHi8;
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case ARM::t2LDRBi12: return ARM::t2LDRBi8;
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case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
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case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
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case ARM::t2STRi12: return ARM::t2STRi8;
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case ARM::t2STRBi12: return ARM::t2STRBi8;
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case ARM::t2STRHi12: return ARM::t2STRHi8;
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case ARM::t2LDRi8:
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case ARM::t2LDRHi8:
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case ARM::t2LDRBi8:
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case ARM::t2LDRSHi8:
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case ARM::t2LDRSBi8:
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case ARM::t2STRi8:
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case ARM::t2STRBi8:
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case ARM::t2STRHi8:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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static unsigned
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positiveOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRi8: return ARM::t2LDRi12;
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case ARM::t2LDRHi8: return ARM::t2LDRHi12;
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case ARM::t2LDRBi8: return ARM::t2LDRBi12;
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case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
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case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
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case ARM::t2STRi8: return ARM::t2STRi12;
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case ARM::t2STRBi8: return ARM::t2STRBi12;
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case ARM::t2STRHi8: return ARM::t2STRHi12;
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case ARM::t2LDRi12:
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case ARM::t2LDRHi12:
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case ARM::t2LDRBi12:
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case ARM::t2LDRSHi12:
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case ARM::t2LDRSBi12:
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case ARM::t2STRi12:
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case ARM::t2STRBi12:
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case ARM::t2STRHi12:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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static unsigned
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immediateOffsetOpcode(unsigned opcode)
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{
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switch (opcode) {
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case ARM::t2LDRs: return ARM::t2LDRi12;
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case ARM::t2LDRHs: return ARM::t2LDRHi12;
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case ARM::t2LDRBs: return ARM::t2LDRBi12;
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case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
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case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
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case ARM::t2STRs: return ARM::t2STRi12;
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case ARM::t2STRBs: return ARM::t2STRBi12;
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case ARM::t2STRHs: return ARM::t2STRHi12;
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case ARM::t2LDRi12:
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case ARM::t2LDRHi12:
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case ARM::t2LDRBi12:
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case ARM::t2LDRSHi12:
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case ARM::t2LDRSBi12:
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case ARM::t2STRi12:
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case ARM::t2STRBi12:
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case ARM::t2STRHi12:
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case ARM::t2LDRi8:
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case ARM::t2LDRHi8:
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case ARM::t2LDRBi8:
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case ARM::t2LDRSHi8:
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case ARM::t2LDRSBi8:
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case ARM::t2STRi8:
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case ARM::t2STRBi8:
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case ARM::t2STRHi8:
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return opcode;
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default:
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break;
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}
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return 0;
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}
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bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, int &Offset,
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const ARMBaseInstrInfo &TII) {
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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bool isSub = false;
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// Memory operands in inline assembly always use AddrModeT2_i12.
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if (Opcode == ARM::INLINEASM)
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AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
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if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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bool isSP = FrameReg == ARM::SP;
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unsigned PredReg;
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if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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// Turn it into a move.
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MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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// Remove offset and remaining explicit predicate operands.
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do MI.RemoveOperand(FrameRegIdx+1);
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while (MI.getNumOperands() > FrameRegIdx+1 &&
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(!MI.getOperand(FrameRegIdx+1).isReg() ||
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!MI.getOperand(FrameRegIdx+1).isImm()));
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return true;
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}
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if (Offset < 0) {
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Offset = -Offset;
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isSub = true;
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MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
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} else {
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MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
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}
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// Common case: small offset, fits into instruction.
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if (ARM_AM::getT2SOImmVal(Offset) != -1) {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
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Offset = 0;
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return true;
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}
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// Another common case: imm12.
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if (Offset < 4096) {
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unsigned NewOpc = isSP
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? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
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: (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
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MI.setDesc(TII.get(NewOpc));
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
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Offset = 0;
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return true;
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}
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// Otherwise, extract 8 adjacent bits from the immediate into this
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// t2ADDri/t2SUBri.
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unsigned RotAmt = CountLeadingZeros_32(Offset);
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unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
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// We will handle these bits from offset, clear them.
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Offset &= ~ThisImmVal;
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assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
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"Bit extraction didn't work?");
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
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} else {
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// AddrMode4 and AddrMode6 cannot handle any offset.
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if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
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return false;
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// AddrModeT2_so cannot handle any offset. If there is no offset
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// register then we change to an immediate version.
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unsigned NewOpc = Opcode;
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if (AddrMode == ARMII::AddrModeT2_so) {
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unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
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if (OffsetReg != 0) {
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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return Offset == 0;
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}
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MI.RemoveOperand(FrameRegIdx+1);
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MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
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NewOpc = immediateOffsetOpcode(Opcode);
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AddrMode = ARMII::AddrModeT2_i12;
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}
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unsigned NumBits = 0;
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unsigned Scale = 1;
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if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
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// i8 supports only negative, and i12 supports only positive, so
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// based on Offset sign convert Opcode to the appropriate
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// instruction
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Offset += MI.getOperand(FrameRegIdx+1).getImm();
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if (Offset < 0) {
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NewOpc = negativeOffsetOpcode(Opcode);
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NumBits = 8;
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isSub = true;
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Offset = -Offset;
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} else {
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NewOpc = positiveOffsetOpcode(Opcode);
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NumBits = 12;
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}
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} else if (AddrMode == ARMII::AddrMode5) {
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// VFP address mode.
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const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
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int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
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if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
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InstrOffs *= -1;
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NumBits = 8;
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Scale = 4;
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Offset += InstrOffs * 4;
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assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
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if (Offset < 0) {
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Offset = -Offset;
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isSub = true;
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}
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} else {
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llvm_unreachable("Unsupported addressing mode!");
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}
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if (NewOpc != Opcode)
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MI.setDesc(TII.get(NewOpc));
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MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
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// Attempt to fold address computation
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// Common case: small offset, fits into instruction.
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with fp/sp
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MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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if (isSub) {
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if (AddrMode == ARMII::AddrMode5)
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// FIXME: Not consistent.
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ImmedOffset |= 1 << NumBits;
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else
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ImmedOffset = -ImmedOffset;
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}
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ImmOp.ChangeToImmediate(ImmedOffset);
|
|
Offset = 0;
|
|
return true;
|
|
}
|
|
|
|
// Otherwise, offset doesn't fit. Pull in what we can to simplify
|
|
ImmedOffset = ImmedOffset & Mask;
|
|
if (isSub) {
|
|
if (AddrMode == ARMII::AddrMode5)
|
|
// FIXME: Not consistent.
|
|
ImmedOffset |= 1 << NumBits;
|
|
else {
|
|
ImmedOffset = -ImmedOffset;
|
|
if (ImmedOffset == 0)
|
|
// Change the opcode back if the encoded offset is zero.
|
|
MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
|
|
}
|
|
}
|
|
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
Offset &= ~(Mask*Scale);
|
|
}
|
|
|
|
Offset = (isSub) ? -Offset : Offset;
|
|
return Offset == 0;
|
|
}
|