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41c5f84f1d
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all operands are zero extended. llvm-svn: 98168
60 lines
1.2 KiB
LLVM
60 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=xcore | FileCheck %s
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define i64 @add64(i64 %a, i64 %b) {
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%result = add i64 %a, %b
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ret i64 %result
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}
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; CHECK: add64
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; CHECK: ldc r11, 0
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; CHECK-NEXT: ladd r2, r0, r0, r2, r11
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; CHECK-NEXT: ladd r2, r1, r1, r3, r2
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; CHECK-NEXT: retsp 0
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define i64 @sub64(i64 %a, i64 %b) {
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%result = sub i64 %a, %b
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ret i64 %result
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}
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; CHECK: sub64
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; CHECK: ldc r11, 0
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; CHECK-NEXT: lsub r2, r0, r0, r2, r11
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; CHECK-NEXT: lsub r2, r1, r1, r3, r2
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; CHECK-NEXT: retsp 0
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define i64 @maccu(i64 %a, i32 %b, i32 %c) {
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entry:
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%0 = zext i32 %b to i64
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%1 = zext i32 %c to i64
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%2 = mul i64 %1, %0
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%3 = add i64 %2, %a
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ret i64 %3
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}
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; CHECK: maccu:
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; CHECK: maccu r1, r0, r3, r2
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; CHECK-NEXT: retsp 0
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define i64 @maccs(i64 %a, i32 %b, i32 %c) {
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entry:
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%0 = sext i32 %b to i64
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%1 = sext i32 %c to i64
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%2 = mul i64 %1, %0
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%3 = add i64 %2, %a
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ret i64 %3
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}
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; CHECK: maccs:
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; CHECK: maccs r1, r0, r3, r2
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; CHECK-NEXT: retsp 0
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define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) {
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entry:
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%0 = zext i32 %a to i64
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%1 = zext i32 %b to i64
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%2 = zext i32 %c to i64
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%3 = zext i32 %d to i64
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%4 = mul i64 %1, %0
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%5 = add i64 %4, %2
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%6 = add i64 %5, %3
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ret i64 %6
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}
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; CHECK: lmul:
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; CHECK: lmul r1, r0, r1, r0, r2, r3
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; CHECK-NEXT: retsp 0
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