Nadav Rotem 008741a0e0 ARM Cost Model: We need to detect the max bitwidth of types in the loop in order to select the max vectorization factor. ... We don't have a detailed analysis on which values are vectorized and which stay scalars in the vectorized loop so we use another method. We look at reduction variables, loads and stores, which are the only ways to get information in and out of loop iterations. If the data types are extended and truncated then the cost model will catch the cost of the vector zext/sext/trunc operations. llvm-svn: 172178		2013-01-11 07:11:59 +00:00
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Hello	Move all of the header files which are involved in modelling the LLVM IR	2013-01-02 11:36:10 +00:00
InstCombine	Teach InstCombine to hoist FABS and FNEG through FPTRUNC instructions. The application of these operations commutes with the truncation, so we should prefer to do them in the smallest size we can, to save register space, use smaller constant pool entries, etc.	2013-01-10 22:06:52 +00:00
Instrumentation	[msan] Change va_start/va_copy shadow memset alignment to 8.	2013-01-10 22:36:33 +00:00
IPO	Fix TryToShrinkGlobalToBoolean in GlobalOpt, so that it does not discard address spaces.	2013-01-10 10:31:11 +00:00
Scalar	PR14904: Segmentation fault running pass 'Recognize loop idioms'	2013-01-10 23:32:01 +00:00
Utils	Make sure we don't emit instructions before a landingpad instruction.	2013-01-08 10:51:32 +00:00
Vectorize	ARM Cost Model: We need to detect the max bitwidth of types in the loop in order to select the max vectorization factor.	2013-01-11 07:11:59 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile