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llvm-mirror/test/CodeGen/ARM/align.ll
Bob Wilson d16aaccb05 Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047
2010-09-29 17:54:10 +00:00

43 lines
708 B
LLVM

; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
@a = global i1 true
; no alignment
@b = global i8 1
; no alignment
@c = global i16 2
;ELF: .align 1
;ELF: c:
;DARWIN: .align 1
;DARWIN: _c:
@d = global i32 3
;ELF: .align 2
;ELF: d:
;DARWIN: .align 2
;DARWIN: _d:
@e = global i64 4
;ELF: .align 3
;ELF: e
;DARWIN: .align 3
;DARWIN: _e:
@f = global float 5.0
;ELF: .align 2
;ELF: f:
;DARWIN: .align 2
;DARWIN: _f:
@g = global double 6.0
;ELF: .align 3
;ELF: g:
;DARWIN: .align 3
;DARWIN: _g:
@bar = common global [75 x i8] zeroinitializer, align 128
;ELF: .comm bar,75,128
;DARWIN: .comm _bar,75,7