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https://github.com/RPCS3/llvm-mirror.git
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0614f2a55e
Summary: There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings. There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those. Reviewers: joerg, aaron.ballman Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15848 llvm-svn: 256707
80 lines
2.8 KiB
LLVM
80 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=i686-unknown-unknown < %s | FileCheck %s
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; RUN: llc -mtriple=i686-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
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%struct.interrupt_frame = type { i32, i32, i32, i32, i32 }
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@llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_clobbers to i8*)], section "llvm.metadata"
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; Spills eax, putting original esp at +4.
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; No stack adjustment if declared with no error code
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define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
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; CHECK-LABEL: test_isr_no_ecode:
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; CHECK: pushl %eax
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; CHECK: movl 12(%esp), %eax
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; CHECK: popl %eax
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; CHECK: iretl
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; CHECK0-LABEL: test_isr_no_ecode:
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; CHECK0: pushl %eax
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; CHECK0: leal 4(%esp), %eax
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; CHECK0: movl 8(%eax), %eax
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; CHECK0: popl %eax
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; CHECK0: iretl
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%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
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%flags = load i32, i32* %pflags, align 4
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call void asm sideeffect "", "r"(i32 %flags)
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ret void
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}
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; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes
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; before return, popping the error code.
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define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i32 %ecode) {
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; CHECK-LABEL: test_isr_ecode
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; CHECK: pushl %ecx
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; CHECK: pushl %eax
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; CHECK: movl 8(%esp), %eax
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; CHECK: movl 20(%esp), %ecx
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; CHECK: popl %eax
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; CHECK: popl %ecx
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; CHECK: addl $4, %esp
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; CHECK: iretl
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; CHECK0-LABEL: test_isr_ecode
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; CHECK0: pushl %ecx
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; CHECK0: pushl %eax
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; CHECK0: movl 8(%esp), %eax
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; CHECK0: leal 12(%esp), %ecx
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; CHECK0: movl 8(%ecx), %ecx
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; CHECK0: popl %eax
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; CHECK0: popl %ecx
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; CHECK0: addl $4, %esp
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; CHECK0: iretl
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%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
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%flags = load i32, i32* %pflags, align 4
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call x86_fastcallcc void asm sideeffect "", "r,r"(i32 %flags, i32 %ecode)
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ret void
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}
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; All clobbered registers must be saved
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define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i32 %ecode) {
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call void asm sideeffect "", "~{eax},~{ebx},~{ebp}"()
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; CHECK-LABEL: test_isr_clobbers
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; CHECK-SSE-NEXT: pushl %ebp
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; CHECK-SSE-NEXT: pushl %ebx
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; CHECK-SSE-NEXT; pushl %eax
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; CHECK-SSE-NEXT: popl %eax
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; CHECK-SSE-NEXT: popl %ebx
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; CHECK-SSE-NEXT: popl %ebp
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; CHECK-SSE-NEXT: addl $4, %esp
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; CHECK-SSE-NEXT: iretl
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; CHECK0-LABEL: test_isr_clobbers
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; CHECK0-SSE-NEXT: pushl %ebp
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; CHECK0-SSE-NEXT: pushl %ebx
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; CHECK0-SSE-NEXT; pushl %eax
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; CHECK0-SSE-NEXT: popl %eax
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; CHECK0-SSE-NEXT: popl %ebx
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; CHECK0-SSE-NEXT: popl %ebp
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; CHECK0-SSE-NEXT: addl $4, %esp
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; CHECK0-SSE-NEXT: iretl
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ret void
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}
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