lewis-revill 32de6fea07 [RISCV] Enable the machine outliner for RISC-V ... This patch enables the machine outliner for RISC-V and adds the necessary logic for checking whether sequences can be safely outlined, and describing how they should be outlined. Outlined functions are called using the register t0 (x5) as the return address register, which must be available for an occurrence of a sequence to be safely outlined. Differential Revision: https://reviews.llvm.org/D66210		2019-12-19 16:41:53 +00:00
..
AArch64	Revert "[AArch64][SVE] Add permutation and selection intrinsics"	2019-12-19 14:26:14 +00:00
AMDGPU	[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr	2019-12-17 18:54:27 +00:00
ARC
ARM	[ARM] Improve codegen of volatile load/store of i64	2019-12-19 11:23:01 +00:00
AVR
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR
MSP430
NVPTX
PowerPC	[PowerPC] Only use PLT annotations if using PIC relocation model	2019-12-19 09:27:13 -06:00
RISCV	[RISCV] Enable the machine outliner for RISC-V	2019-12-19 16:41:53 +00:00
SPARC
SystemZ	[FPEnv] Strict versions of llvm.minimum/llvm.maximum	2019-12-18 21:35:28 +01:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Add avgr_u intrinsics and require nuw in patterns	2019-12-18 15:31:38 -08:00
WinCFGuard
WinEH
X86	Enable STRICT_FP_TO_SINT/UINT on X86 backend	2019-12-19 14:49:13 +08:00
XCore