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https://github.com/RPCS3/llvm-mirror.git
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7fc741759e
Add the ARC backend as an experimental target to lib/Target. Reviewed at: https://reviews.llvm.org/D36331 llvm-svn: 311667
256 lines
5.1 KiB
LLVM
256 lines
5.1 KiB
LLVM
; RUN: llc -march=arc < %s | FileCheck %s
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; CHECK-LABEL: add_r
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; CHECK: add %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @add_r(i32 %a, i32 %b) nounwind {
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entry:
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%v = add i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: add_u6
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; CHECK: add %r0, %r0, 15
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define i32 @add_u6(i32 %a) nounwind {
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%v = add i32 %a, 15
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ret i32 %v
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}
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; CHECK-LABEL: add_limm
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; CHECK: add %r0, %r0, 12345
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define i32 @add_limm(i32 %a) nounwind {
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%v = add i32 %a, 12345
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ret i32 %v
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}
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; CHECK-LABEL: mpy_r
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; CHECK: mpy %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @mpy_r(i32 %a, i32 %b) nounwind {
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entry:
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%v = mul i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: mpy_u6
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; CHECK: mpy %r0, %r0, 10
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define i32 @mpy_u6(i32 %a) nounwind {
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%v = mul i32 %a, 10
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ret i32 %v
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}
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; CHECK-LABEL: mpy_limm
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; CHECK: mpy %r0, %r0, 12345
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define i32 @mpy_limm(i32 %a) nounwind {
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%v = mul i32 %a, 12345
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ret i32 %v
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}
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; CHECK-LABEL: max_r
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; CHECK: max %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @max_r(i32 %a, i32 %b) nounwind {
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%i = icmp sgt i32 %a, %b
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%v = select i1 %i, i32 %a, i32 %b
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ret i32 %v
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}
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; CHECK-LABEL: max_u6
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; CHECK: max %r0, %r0, 12
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define i32 @max_u6(i32 %a) nounwind {
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%i = icmp sgt i32 %a, 12
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%v = select i1 %i, i32 %a, i32 12
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ret i32 %v
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}
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; CHECK-LABEL: max_limm
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; CHECK: max %r0, %r0, 2345
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define i32 @max_limm(i32 %a) nounwind {
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%i = icmp sgt i32 %a, 2345
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%v = select i1 %i, i32 %a, i32 2345
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ret i32 %v
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}
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; CHECK-LABEL: min_r
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; CHECK: min %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @min_r(i32 %a, i32 %b) nounwind {
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%i = icmp slt i32 %a, %b
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%v = select i1 %i, i32 %a, i32 %b
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ret i32 %v
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}
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; CHECK-LABEL: min_u6
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; CHECK: min %r0, %r0, 20
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define i32 @min_u6(i32 %a) nounwind {
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%i = icmp slt i32 %a, 20
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%v = select i1 %i, i32 %a, i32 20
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ret i32 %v
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}
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; CHECK-LABEL: min_limm
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; CHECK: min %r0, %r0, 2040
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define i32 @min_limm(i32 %a) nounwind {
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%i = icmp slt i32 %a, 2040
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%v = select i1 %i, i32 %a, i32 2040
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ret i32 %v
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}
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; CHECK-LABEL: and_r
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; CHECK: and %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @and_r(i32 %a, i32 %b) nounwind {
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%v = and i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: and_u6
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; CHECK: and %r0, %r0, 7
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define i32 @and_u6(i32 %a) nounwind {
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%v = and i32 %a, 7
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ret i32 %v
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}
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; 0xfffff == 1048575
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; CHECK-LABEL: and_limm
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; CHECK: and %r0, %r0, 1048575
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define i32 @and_limm(i32 %a) nounwind {
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%v = and i32 %a, 1048575
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ret i32 %v
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}
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; CHECK-LABEL: or_r
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; CHECK: or %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @or_r(i32 %a, i32 %b) nounwind {
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%v = or i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: or_u6
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; CHECK: or %r0, %r0, 7
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define i32 @or_u6(i32 %a) nounwind {
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%v = or i32 %a, 7
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ret i32 %v
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}
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; 0xf0f0f == 986895
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; CHECK-LABEL: or_limm
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define i32 @or_limm(i32 %a) nounwind {
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%v = or i32 %a, 986895
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ret i32 %v
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}
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; CHECK-LABEL: xor_r
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; CHECK: xor %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @xor_r(i32 %a, i32 %b) nounwind {
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%v = xor i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: xor_u6
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; CHECK: xor %r0, %r0, 3
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define i32 @xor_u6(i32 %a) nounwind {
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%v = xor i32 %a, 3
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ret i32 %v
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}
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; CHECK-LABEL: xor_limm
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; CHECK: xor %r0, %r0, 986895
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define i32 @xor_limm(i32 %a) nounwind {
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%v = xor i32 %a, 986895
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ret i32 %v
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}
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; CHECK-LABEL: asl_r
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; CHECK: asl %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @asl_r(i32 %a, i32 %b) nounwind {
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%v = shl i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: asl_u6
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; CHECK: asl %r0, %r0, 4
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define i32 @asl_u6(i32 %a) nounwind {
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%v = shl i32 %a, 4
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ret i32 %v
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}
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; CHECK-LABEL: lsr_r
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; CHECK: lsr %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @lsr_r(i32 %a, i32 %b) nounwind {
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%v = lshr i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: lsr_u6
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; CHECK: lsr %r0, %r0, 6
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define i32 @lsr_u6(i32 %a) nounwind {
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%v = lshr i32 %a, 6
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ret i32 %v
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}
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; CHECK-LABEL: asr_r
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; CHECK: asr %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @asr_r(i32 %a, i32 %b) nounwind {
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%v = ashr i32 %a, %b
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ret i32 %v
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}
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; CHECK-LABEL: asr_u6
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; CHECK: asr %r0, %r0, 8
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define i32 @asr_u6(i32 %a) nounwind {
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%v = ashr i32 %a, 8
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ret i32 %v
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}
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; CHECK-LABEL: ror_r
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; CHECK: ror %r0, %r{{[01]}}, %r{{[01]}}
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define i32 @ror_r(i32 %a, i32 %b) nounwind {
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%v1 = lshr i32 %a, %b
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%ls = sub i32 32, %b
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%v2 = shl i32 %a, %ls
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%v = or i32 %v1, %v2
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ret i32 %v
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}
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; CHECK-LABEL: ror_u6
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; CHECK: ror %r0, %r0, 10
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define i32 @ror_u6(i32 %a) nounwind {
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%v1 = lshr i32 %a, 10
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%v2 = shl i32 %a, 22
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%v = or i32 %v1, %v2
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ret i32 %v
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}
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; CHECK-LABEL: sexh_r
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; CHECK: sexh %r0, %r0
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define i32 @sexh_r(i32 %a) nounwind {
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%v1 = shl i32 %a, 16
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%v = ashr i32 %v1, 16
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ret i32 %v
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}
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; CHECK-LABEL: sexb_r
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; CHECK: sexb %r0, %r0
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define i32 @sexb_r(i32 %a) nounwind {
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%v1 = shl i32 %a, 24
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%v = ashr i32 %v1, 24
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ret i32 %v
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}
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; CHECK-LABEL: mulu64
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; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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; CHECK-DAG: mpymu %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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define i64 @mulu64(i32 %a, i32 %b) nounwind {
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%a64 = zext i32 %a to i64
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%b64 = zext i32 %b to i64
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%v = mul i64 %a64, %b64
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ret i64 %v
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}
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; CHECK-LABEL: muls64
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; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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; CHECK-DAG: mpym %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
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define i64 @muls64(i32 %a, i32 %b) nounwind {
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%a64 = sext i32 %a to i64
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%b64 = sext i32 %b to i64
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%v = mul i64 %a64, %b64
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ret i64 %v
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}
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