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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
103 lines
3.4 KiB
YAML
103 lines
3.4 KiB
YAML
# RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o - %s | FileCheck %s
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# This test ensures that the MIR parser parses the call entry pseudo source
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# values in memory operands correctly.
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--- |
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define i32 @test(i32 %a) {
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entry:
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%call = call i32 @foo(i32 %a)
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ret i32 0
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}
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declare i32 @foo(i32)
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define float @test2() #0 {
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entry:
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%call = tail call float bitcast (float (...)* @g to float ()*)()
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call void @__mips16_ret_sf(float %call)
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ret float %call
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}
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declare float @g(...)
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declare void @__mips16_ret_sf(float) #1
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attributes #0 = { "saveS2" }
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attributes #1 = { noinline readnone "__Mips16RetHelper" }
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...
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---
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name: test
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tracksRegLiveness: true
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liveins:
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- { reg: '$a0' }
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frameInfo:
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stackSize: 24
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 16
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stack:
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- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
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callee-saved-register: '$ra' }
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body: |
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bb.0.entry:
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liveins: $a0, $ra
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Save16 $ra, 24, implicit-def $sp, implicit $sp
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CFI_INSTRUCTION def_cfa_offset 24
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CFI_INSTRUCTION offset $ra_64, -4
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$v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
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$v0 = SllX16 killed $v0, 16
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$v0 = AdduRxRyRz16 killed $v1, killed $v0
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; CHECK-LABEL: name: test
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; CHECK: $v1 = LwRxRyOffMemX16 $v0, @foo :: (load 4 from call-entry @foo)
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$v1 = LwRxRyOffMemX16 $v0, @foo :: (load 4 from call-entry @foo)
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$t9 = COPY $v1
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$gp = COPY killed $v0
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JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit killed $gp, implicit-def $sp, implicit-def dead $v0
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$v0 = LiRxImmX16 0
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$ra = Restore16 24, implicit-def $sp, implicit $sp
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RetRA16 implicit $v0
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...
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---
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name: test2
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tracksRegLiveness: true
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frameInfo:
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stackSize: 32
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 16
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stack:
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- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
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callee-saved-register: '$ra' }
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- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4,
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callee-saved-register: '$s2' }
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- { id: 2, type: spill-slot, offset: -12, size: 4, alignment: 4,
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callee-saved-register: '$s0' }
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body: |
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bb.0.entry:
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liveins: $ra, $s2, $s0, $ra, $s2, $s0
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SaveX16 $s0, $ra, $s2, 32, implicit-def $sp, implicit $sp
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CFI_INSTRUCTION def_cfa_offset 32
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CFI_INSTRUCTION offset $ra_64, -4
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CFI_INSTRUCTION offset $s2_64, -8
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CFI_INSTRUCTION offset $s0_64, -12
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$v0, $v1 = GotPrologue16 &_gp_disp, &_gp_disp
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$v0 = SllX16 killed $v0, 16
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$s0 = AdduRxRyRz16 killed $v1, killed $v0
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$v0 = LwRxRyOffMemX16 $s0, @g :: (load 4 from call-entry @g)
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; CHECK-LABEL: test2
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; CHECK: $v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0)
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$v1 = LwRxRyOffMemX16 $s0, &__mips16_call_stub_sf_0 :: (load 4 from call-entry &__mips16_call_stub_sf_0)
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$gp = COPY $s0
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JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit $v0, implicit killed $gp, implicit-def $sp, implicit-def $v0
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$v1 = LwRxRyOffMemX16 $s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf)
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$t9 = COPY $v1
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$gp = COPY killed $s0
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JumpLinkReg16 killed $v1, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $v0, implicit killed $gp, implicit-def $sp
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$s0, $ra, $s2 = RestoreX16 32, implicit-def $sp, implicit $sp
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RetRA16 implicit $v0
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...
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