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3307a878a0
llvm-mirror/test/CodeGen
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Alex Lorenz 3307a878a0 MIR Serialization: Serialize the virtual register operands. 
Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D11005

llvm-svn: 241959
2015-07-10 22:51:20 +00:00
..
AArch64 [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks. 2015-07-10 22:09:55 +00:00
AMDGPU DAGCombiner: Assume invariant load cannot alias a store 2015-07-10 22:17:40 +00:00
ARM ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code 2015-07-10 18:37:33 +00:00
BPF
CPP
Generic llc: Add a 'run-pass' option. 2015-07-06 17:44:26 +00:00
Hexagon [Hexagon] Add support for atomic RMW operations 2015-07-09 14:51:21 +00:00
Inputs
Mips
MIR MIR Serialization: Serialize the virtual register operands. 2015-07-10 22:51:20 +00:00
MSP430
NVPTX Actually support volatile memcpys in NVPTX lowering 2015-07-10 15:40:33 +00:00
PowerPC Add missing builtins to the PPC back end for ABI compliance (vol. 2) 2015-07-05 06:03:51 +00:00
SPARC [SPARC] Cleanup handling of the Y/ASR registers. 2015-07-08 16:25:12 +00:00
SystemZ
Thumb
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-10 18:28:49 +00:00
WebAssembly [WebAssembly] Create a CodeGen unittest directory. 2015-07-06 23:14:57 +00:00
WinEH [SEH] Push reloads of the SEH code past phi nodes 2015-07-10 22:21:54 +00:00
X86 [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks. 2015-07-10 22:09:55 +00:00
XCore