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76 lines
3.3 KiB
LLVM
76 lines
3.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; This should end with an no-op sequence of exec mask manipulations
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; Mask should be in original state after executed unreachable block
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; GCN-LABEL: {{^}}main:
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; GCN: s_cbranch_scc1 [[RET_BB:BB[0-9]+_[0-9]+]]
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; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN-NEXT: s_xor_b64 [[XOR_EXEC:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_EXEC]]
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; GCN-NEXT: ; mask branch [[UNREACHABLE_BB:BB[0-9]+_[0-9]+]]
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; GCN: [[RET_BB]]:
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; GCN-NEXT: s_branch [[FINAL_BB:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[UNREACHABLE_BB]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]]
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; GCN-NEXT: [[FINAL_BB]]:
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; GCN-NEXT: .Lfunc_end0
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define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <8 x i32>] addrspace(2)* byval %arg2, i32 addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
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main_body:
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%i.i = extractelement <2 x i32> %arg7, i32 0
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%j.i = extractelement <2 x i32> %arg7, i32 1
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%i.f.i = bitcast i32 %i.i to float
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%j.f.i = bitcast i32 %j.i to float
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%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #2
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%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
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%p87 = fmul float undef, %p2.i
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%p88 = fadd float %p87, undef
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%p93 = fadd float %p88, undef
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%p97 = fmul float %p93, undef
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%p102 = fsub float %p97, undef
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%p104 = fmul float %p102, undef
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%p106 = fadd float 0.000000e+00, %p104
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%p108 = fadd float undef, %p106
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br i1 undef, label %ENDIF69, label %ELSE
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ELSE: ; preds = %main_body
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%p124 = fmul float %p108, %p108
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%p125 = fsub float %p124, undef
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%p126 = fcmp olt float %p125, 0.000000e+00
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br i1 %p126, label %ENDIF69, label %ELSE41
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ELSE41: ; preds = %ELSE
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unreachable
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ENDIF69: ; preds = %ELSE, %main_body
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ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.fabs.f32(float) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.sqrt.f32(float) #1
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; Function Attrs: nounwind readnone
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declare float @llvm.floor.f32(float) #1
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attributes #0 = { "InitialPSInputAddr"="36983" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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