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faad462651
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
(v4i32 (uaddv ...))
is the same as
(v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
(i32 (int_aarch64_neon_uaddv ...)), ssub)
In a combine, we transform all such across-vector-lanes intrinsics to:
(i32 (extract_vector_elt (uaddv ...), 0))
This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs. Consider:
uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
return vmulq_n_u32(a, vaddvq_u32(b));
}
We now generate:
addv.4s s1, v1
mul.4s v0, v0, v1[0]
instead of the previous:
addv.4s s1, v1
fmov w8, s1
dup.4s v1, w8
mul.4s v0, v1, v0
rdar://20044838
llvm-svn: 231840
165 lines
5.2 KiB
LLVM
165 lines
5.2 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u8x8:
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; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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declare i32 @bar(...)
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define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u4x16:
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; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i16
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%tobool = icmp eq i16 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u8x16:
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; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i16
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%tobool = icmp eq i16 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp {
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; CHECK-LABEL: vmax_u16x8:
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; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
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; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
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; CHECK-NOT: and
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; CHECK: cbz [[REG2]],
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entry:
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%vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
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%tmp = trunc i32 %vmaxv.i to i8
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%tobool = icmp eq i8 %tmp, 0
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br i1 %tobool, label %return, label %if.then
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if.then:
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%call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
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br label %return
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return:
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%retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:
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; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <8 x i8> %a1, i8 %1, i32 3
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ret <8 x i8> %2
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}
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define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
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; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:
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; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <4 x i16> %a1, i16 %1, i32 3
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ret <4 x i16> %2
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}
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define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
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; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:
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; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1
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; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)
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%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
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ret <2 x i32> %1
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}
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define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:
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; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <16 x i8> %a1, i8 %1, i32 3
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ret <16 x i8> %2
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}
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define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop:
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; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <8 x i16> %a1, i16 %1, i32 3
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ret <8 x i16> %2
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}
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define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop:
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; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)
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%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
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ret <4 x i32> %1
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}
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declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone
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declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone
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