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https://github.com/RPCS3/llvm-mirror.git
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9eac1de1e4
There's probably no acatual change in behaviour here, just updating the LowerFP_TO_INT function to be more similar to the reverse implementation and updating costs to current CodeGen. llvm-svn: 210985
142 lines
3.8 KiB
LLVM
142 lines
3.8 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define <2 x i64> @test_v2f32_to_signed_v2i64(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_signed_v2i64:
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; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
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; CHECK: fcvtzs.2d v0, [[VAL64]]
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%val = fptosi <2 x float> %in to <2 x i64>
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ret <2 x i64> %val
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}
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define <2 x i64> @test_v2f32_to_unsigned_v2i64(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_unsigned_v2i64:
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; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
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; CHECK: fcvtzu.2d v0, [[VAL64]]
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%val = fptoui <2 x float> %in to <2 x i64>
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ret <2 x i64> %val
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}
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define <2 x i16> @test_v2f32_to_signed_v2i16(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_signed_v2i16:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptosi <2 x float> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i16> @test_v2f32_to_unsigned_v2i16(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_unsigned_v2i16:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptoui <2 x float> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i8> @test_v2f32_to_signed_v2i8(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_signed_v2i8:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptosi <2 x float> %in to <2 x i8>
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ret <2 x i8> %val
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}
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define <2 x i8> @test_v2f32_to_unsigned_v2i8(<2 x float> %in) {
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; CHECK-LABEL: test_v2f32_to_unsigned_v2i8:
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; CHECK: fcvtzs.2s v0, v0
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%val = fptoui <2 x float> %in to <2 x i8>
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ret <2 x i8> %val
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}
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define <4 x i16> @test_v4f32_to_signed_v4i16(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_signed_v4i16:
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; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptosi <4 x float> %in to <4 x i16>
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ret <4 x i16> %val
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}
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define <4 x i16> @test_v4f32_to_unsigned_v4i16(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_unsigned_v4i16:
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; CHECK: fcvtzu.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptoui <4 x float> %in to <4 x i16>
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ret <4 x i16> %val
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}
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define <4 x i8> @test_v4f32_to_signed_v4i8(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_signed_v4i8:
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; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptosi <4 x float> %in to <4 x i8>
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ret <4 x i8> %val
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}
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define <4 x i8> @test_v4f32_to_unsigned_v4i8(<4 x float> %in) {
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; CHECK-LABEL: test_v4f32_to_unsigned_v4i8:
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; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.4h v0, [[VAL64]]
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%val = fptoui <4 x float> %in to <4 x i8>
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ret <4 x i8> %val
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}
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define <2 x i32> @test_v2f64_to_signed_v2i32(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_signed_v2i32:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptosi <2 x double> %in to <2 x i32>
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ret <2 x i32> %val
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}
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define <2 x i32> @test_v2f64_to_unsigned_v2i32(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_unsigned_v2i32:
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; CHECK: fcvtzu.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptoui <2 x double> %in to <2 x i32>
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ret <2 x i32> %val
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}
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define <2 x i16> @test_v2f64_to_signed_v2i16(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_signed_v2i16:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptosi <2 x double> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i16> @test_v2f64_to_unsigned_v2i16(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_unsigned_v2i16:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptoui <2 x double> %in to <2 x i16>
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ret <2 x i16> %val
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}
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define <2 x i8> @test_v2f64_to_signed_v2i8(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_signed_v2i8:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptosi <2 x double> %in to <2 x i8>
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ret <2 x i8> %val
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}
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define <2 x i8> @test_v2f64_to_unsigned_v2i8(<2 x double> %in) {
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; CHECK-LABEL: test_v2f64_to_unsigned_v2i8:
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; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
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; CHECK: xtn.2s v0, [[VAL64]]
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%val = fptoui <2 x double> %in to <2 x i8>
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ret <2 x i8> %val
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}
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