Tom Stellard 33ad0a78c5 R600/SI: Define a schedule model and enable the generic machine scheduler ... The schedule model is not complete yet, and could be improved. llvm-svn: 227461		2015-01-29 16:55:25 +00:00
..
AArch64	[AArch64][LoadStoreOptimizer] Form LDPSW when possible.	2015-01-24 01:25:54 +00:00
ARM	Add a missing Tag_DIV_use test for Cortex-M7.	2015-01-29 11:19:54 +00:00
BPF	bpf: add missing lit.local.cfg	2015-01-24 18:20:52 +00:00
CPP
Generic	overloaded-intrinsic-name: exercise anyptr on struct	2015-01-27 20:03:08 +00:00
Hexagon	[Hexagon] Adding XTYPE/PRED intrinsic tests. Converting predicate types to i32 instead of i1.	2015-01-29 16:08:43 +00:00
Inputs
Mips	Move the Mips target to storing the ABI in the TargetMachine rather	2015-01-26 17:33:46 +00:00
MSP430
NVPTX	[NVPTX] Generate a more optimal sequence for select of i1	2015-01-26 19:52:20 +00:00
PowerPC	[PowerPC] Complete setting the baseline for ppc64le	2015-01-29 15:59:09 +00:00
R600	R600/SI: Define a schedule model and enable the generic machine scheduler	2015-01-29 16:55:25 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[X86] Use single add/sub for large stack offsets	2015-01-29 16:18:29 +00:00
XCore