Justin Bogner b7a198f7fd NVPTX: Remove the legacy ptx intrinsics ... - Rename the ptx.read.* intrinsics to nvvm.read.ptx.sreg.* - some but not all of these registers were already accessible via the nvvm name. - Rename ptx.bar.sync nvvm.bar.sync, to match nvvm.bar0. There's a fair amount of code motion here, but it's all very mechanical. llvm-svn: 274769		2016-07-07 16:40:17 +00:00
..
access-non-generic.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
add-128bit.ll
addrspacecast-gvar.ll
addrspacecast.ll
aggr-param.ll
alias.ll
annotations.ll
arg-lowering.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll
atomics.ll
bfe.ll
branch-fold.ll
bug17709.ll
bug21465.ll	Revert r273313 "[NVPTX] Improve lowering of byval args of device functions."	2016-06-29 20:51:15 +00:00
bug22246.ll
bug22322.ll	NVPTX: Remove the legacy ptx intrinsics	2016-07-07 16:40:17 +00:00
bug26185-2.ll	[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection	2016-05-02 18:12:02 +00:00
bug26185.ll	[NVPTX] Handle ldg created from sign-/zero-extended load	2016-04-05 12:38:01 +00:00
bypass-div.ll
call-with-alloca-buffer.ll
callchain.ll
calling-conv.ll
combine-min-max.ll
compare-int.ll
constant-vectors.ll
convergent-mir-call.ll
convert-fp.ll
convert-int-sm20.ll
ctlz.ll
ctpop.ll
cttz.ll
debug-file-loc.ll	[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.	2016-04-15 15:57:41 +00:00
disable-opt.ll
div-ri.ll
envreg.ll
extloadv.ll
fast-math.ll
fma-assoc.ll
fma-disable.ll
fma.ll
fp16.ll
fp-contract.ll
fp-literals.ll
function-align.ll
generic-to-nvvm.ll
global-addrspace.ll
global-ctor-empty.ll
global-ctor.ll
global-dtor.ll
global-ordering.ll
global-visibility.ll
globals_init.ll
globals_lowering.ll
gvar-init.ll
half.ll
i1-global.ll
i1-int-to-fp.ll
i1-param.ll
i8-param.ll
imad.ll
implicit-def.ll
inline-asm.ll
intrin-nocapture.ll
intrinsic-old.ll	NVPTX: Remove the legacy ptx intrinsics	2016-07-07 16:40:17 +00:00
intrinsics.ll
isspacep.ll
ld-addrspace.ll
ld-generic.ll
ldparam-v4.ll
ldu-i8.ll
ldu-ldg.ll
ldu-reg-plus-offset.ll
lit.local.cfg
load-sext-i1.ll
load-with-non-coherent-cache.ll
local-stack-frame.ll
loop-vectorize.ll
lower-aggr-copies.ll
lower-alloca.ll
lower-kernel-ptr-arg.ll	Revert r273313 "[NVPTX] Improve lowering of byval args of device functions."	2016-06-29 20:51:15 +00:00
machine-sink.ll
MachineSink-call.ll
MachineSink-convergent.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
managed.ll
misaligned-vector-ldst.ll
module-inline-asm.ll
mulwide.ll
noduplicate-syncthreads.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
nounroll.ll
nvcl-param-align.ll
nvvm-reflect-module-flag.ll
nvvm-reflect.ll
param-align.ll
pr13291-i1-store.ll
pr16278.ll
pr17529.ll
refl1.ll
reg-copy.ll
rotate.ll
rsqrt.ll
sched1.ll
sched2.ll
sext-in-reg.ll
sext-params.ll
shfl.ll	[NVPTX] Add intrinsics for shfl instructions.	2016-06-09 20:04:08 +00:00
shift-parts.ll
simple-call.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-32.ll
sm-version-35.ll
sm-version-37.ll
sm-version-50.ll
sm-version-52.ll
sm-version-53.ll
sm-version-60.ll	[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.	2016-07-06 21:06:10 +00:00
sm-version-61.ll	[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.	2016-07-06 21:06:10 +00:00
sm-version-62.ll	[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.	2016-07-06 21:06:10 +00:00
speculative-execution-divergent-target.ll	Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.	2016-04-15 01:20:52 +00:00
st-addrspace.ll
st-generic.ll
surf-read-cuda.ll
surf-read.ll
surf-write-cuda.ll
surf-write.ll
symbol-naming.ll
TailDuplication-convergent.ll	NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0	2016-07-06 20:02:45 +00:00
tex-read-cuda.ll
tex-read.ll
texsurf-queries.ll
tuple-literal.ll
vec8.ll
vec-param-load.ll
vector-args.ll
vector-call.ll
vector-compare.ll
vector-global.ll
vector-loads.ll
vector-return.ll
vector-select.ll
vector-stores.ll
weak-global.ll
weak-linkage.ll
zeroext-32bit.ll	Only emit extension for zeroext/signext arguments if type is < 32 bits	2016-06-27 20:22:22 +00:00