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13c5bb4a2e
Presently, CodeGenPrepare deletes all nearly empty (only phi and branch) basic blocks. This pass can delete loop preheaders which frequently creates critical edges. A preheader can be a convenient place to spill registers to the stack. If the entrance to a loop body is a critical edge, then spills may occur in the loop body rather than immediately before it. This patch protects loop preheaders from deletion in CodeGenPrepare even if they are nearly empty. Since the patch alters the CFG, it affects a large number of test cases. In most cases, the changes are merely cosmetic (basic blocks have different names or instruction orders change slightly). I am somewhat concerned about the test/CodeGen/Mips/brdelayslot.ll test case. If the loop preheader is not deleted, then the MIPS backend does not take advantage of a branch delay slot. Consequently, I would like some close review by a MIPS expert. The patch also partially subsumes D16893 from George Burgess IV. George correctly notes that CodeGenPrepare does not actually preserve the dominator tree. I think the dominator tree was usually not valid when CodeGenPrepare ran, but I am using LoopInfo to mark preheaders, so the dominator tree is now always valid before CodeGenPrepare. Author: Tom Jablin (tjablin) Reviewers: hfinkel george.burgess.iv vkalintiris dsanders kbarton cycheng http://reviews.llvm.org/D16984 llvm-svn: 265397
196 lines
7.9 KiB
LLVM
196 lines
7.9 KiB
LLVM
; RUN: llc < %s -march=x86 -disable-block-placement | FileCheck %s
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;
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; Test RegistersDefinedFromSameValue. We have multiple copies of the same vreg:
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; while.body85.i:
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; vreg1 = copy vreg2
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; vreg2 = add
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; critical edge from land.lhs.true.i -> if.end117.i:
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; vreg27 = vreg2
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; critical edge from land.lhs.true103.i -> if.end117.i:
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; vreg27 = vreg2
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; if.then108.i:
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; vreg27 = vreg1
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;
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; Prior to fixing PR10920 401.bzip miscompile, the coalescer would
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; consider vreg1 and vreg27 to be copies of the same value. It would
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; then remove one of the critical edge copes, which cannot safely be removed.
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; There are two obvious ways the register-allocator could go here, either
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; reusing the pre-addition register later, or the post-addition one. Currently,
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; it does the latter, so we check:
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; CHECK: # %while.body85.i{{$}}
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; CHECK-NOT: # %
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; CHECK-NOT: add
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; CHECK: movl %[[POSTR:e[abcdxi]+]], %[[PRER:e[abcdxi]+]]
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; CHECK: addl %{{.*}}, %[[POSTR]]
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; CHECK: # %while.end.i
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; CHECK-NOT: movl %[[POSTR]]
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; CHECK: # %land.lhs.true.i
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; CHECK-NOT: movl %[[POSTR]]
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; CHECK: # %land.lhs.true103.i
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; CHECK-NOT: movl %[[POSTR]]
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; CHECK: # %if.then108.i
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; CHECK: movl %[[PRER]], %[[POSTR]]
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; CHECK: # %if.end117.i
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; and use it for fprintf:
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; CHECK: movl %[[POSTR]], 12(%esp)
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; If it ever reverts to reusing the pre-addition register then we should
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; *probably* check this instead (it certainly worked last time):
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; CHECKALT: # %while.body85.i
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; CHECKALT-NOT: # %
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; CHECKALT-NOT: add
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; CHECKALT: movl %[[POSTR:e[abcdxi]+]], %[[PRER:e[abcdxi]+]]
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; CHECKALT: addl %{{.*}}, %[[POSTR]]
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; CHECKALT: # %while.end.i
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; CHECKALT: movl %[[POSTR]], %[[USER:e[abcdxi]+]]
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; CHECKALT: # %land.lhs.true.i
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; CHECKALT: movl %[[POSTR]], %[[USER]]
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; CHECKALT: # %land.lhs.true103.i
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; CHECKALT: movl %[[POSTR]], %[[USER]]
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; CHECKALT: # %if.then108.i
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; [[PRER] live out, so nothing on this path should define it.
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; CHECKALT-NOT: , %[[PRER]]
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; CHECKALT: # %if.end117.i
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
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@.str3 = external unnamed_addr constant [59 x i8], align 1
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define void @BZ2_compressBlock() nounwind ssp {
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entry:
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br i1 undef, label %if.then68, label %if.end85
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if.then68: ; preds = %entry
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br label %for.body.i.i
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for.body.i.i: ; preds = %for.inc.i.i, %if.then68
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br i1 undef, label %for.inc.i.i, label %if.then.i.i
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if.then.i.i: ; preds = %for.body.i.i
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br label %for.inc.i.i
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for.inc.i.i: ; preds = %if.then.i.i, %for.body.i.i
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br i1 undef, label %makeMaps_e.exit.i, label %for.body.i.i
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makeMaps_e.exit.i: ; preds = %for.inc.i.i
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br i1 undef, label %for.cond19.preheader.i, label %for.cond.for.cond19.preheader_crit_edge.i
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for.cond.for.cond19.preheader_crit_edge.i: ; preds = %makeMaps_e.exit.i
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unreachable
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for.cond19.preheader.i: ; preds = %makeMaps_e.exit.i
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br i1 undef, label %for.body25.lr.ph.i, label %for.cond33.preheader.i
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for.body25.lr.ph.i: ; preds = %for.cond19.preheader.i
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br label %for.body25.i
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for.cond33.preheader.i: ; preds = %for.body25.i, %for.cond19.preheader.i
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br i1 undef, label %if.then.i, label %if.end.i
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for.body25.i: ; preds = %for.body25.i, %for.body25.lr.ph.i
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br i1 undef, label %for.body25.i, label %for.cond33.preheader.i
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if.then.i: ; preds = %for.cond33.preheader.i
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br label %if.end.i
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if.end.i: ; preds = %if.then.i, %for.cond33.preheader.i
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br i1 undef, label %for.inc27.us.5.i, label %for.end30.i
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for.end30.i: ; preds = %for.inc27.us.5.i, %if.end.i
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br i1 undef, label %if.end36.i, label %if.then35.i
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if.then35.i: ; preds = %for.end30.i
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unreachable
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if.end36.i: ; preds = %for.end30.i
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%sub83.i = add nsw i32 undef, 1
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br label %while.body.i188
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for.cond182.preheader.i: ; preds = %for.end173.i
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br i1 undef, label %for.inc220.us.i, label %while.body300.preheader.i
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while.body.i188: ; preds = %for.end173.i, %if.end36.i
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%gs.0526.i = phi i32 [ 0, %if.end36.i ], [ %add177.i, %for.end173.i ]
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%or.cond514517.i = and i1 false, undef
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br i1 %or.cond514517.i, label %while.body85.i, label %if.end117.i
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while.body85.i: ; preds = %while.body85.i, %while.body.i188
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%aFreq.0518.i = phi i32 [ %add93.i, %while.body85.i ], [ 0, %while.body.i188 ]
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%inc87.i = add nsw i32 0, 1
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%tmp91.i = load i32, i32* undef, align 4
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%add93.i = add nsw i32 %tmp91.i, %aFreq.0518.i
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%or.cond514.i = and i1 undef, false
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br i1 %or.cond514.i, label %while.body85.i, label %while.end.i
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while.end.i: ; preds = %while.body85.i
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br i1 undef, label %land.lhs.true.i, label %if.end117.i
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land.lhs.true.i: ; preds = %while.end.i
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br i1 undef, label %land.lhs.true103.i, label %if.end117.i
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land.lhs.true103.i: ; preds = %land.lhs.true.i
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br i1 undef, label %if.then108.i, label %if.end117.i
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if.then108.i: ; preds = %land.lhs.true103.i
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br label %if.end117.i
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if.end117.i: ; preds = %if.then108.i, %land.lhs.true103.i, %land.lhs.true.i, %while.end.i, %while.body.i188
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%aFreq.1.i = phi i32 [ %aFreq.0518.i, %if.then108.i ], [ %add93.i, %land.lhs.true103.i ], [ %add93.i, %land.lhs.true.i ], [ %add93.i, %while.end.i ], [ 0, %while.body.i188 ]
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%ge.1.i = phi i32 [ 0, %if.then108.i ], [ %inc87.i, %land.lhs.true103.i ], [ %inc87.i, %land.lhs.true.i ], [ %inc87.i, %while.end.i ], [ 0, %while.body.i188 ]
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br i1 undef, label %if.then122.i, label %for.cond138.preheader.i
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if.then122.i: ; preds = %if.end117.i
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call void (...) @fprintf(i32 undef, i32 %gs.0526.i, i32 %ge.1.i, i32 %aFreq.1.i, double undef) nounwind
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br label %for.cond138.preheader.i
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for.cond138.preheader.i: ; preds = %if.then122.i, %if.end117.i
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br i1 undef, label %for.body143.lr.ph.i, label %for.end173.i
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for.body143.lr.ph.i: ; preds = %for.cond138.preheader.i
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br label %for.body143.i
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for.body143.i: ; preds = %for.body143.i, %for.body143.lr.ph.i
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br i1 undef, label %for.end173.i, label %for.body143.i
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for.end173.i: ; preds = %for.body143.i, %for.cond138.preheader.i
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%add177.i = add nsw i32 %ge.1.i, 1
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%cmp73.i = icmp sgt i32 undef, 0
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br i1 %cmp73.i, label %while.body.i188, label %for.cond182.preheader.i
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for.inc220.us.i: ; preds = %for.cond182.preheader.i
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unreachable
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while.body300.preheader.i: ; preds = %for.cond182.preheader.i
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br i1 undef, label %for.end335.i, label %while.end2742.i
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for.end335.i: ; preds = %for.end2039.i, %while.body300.preheader.i
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br label %for.body2021.i
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for.body2021.i: ; preds = %for.body2021.i, %for.end335.i
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br i1 undef, label %for.body2021.i, label %for.end2039.i
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for.end2039.i: ; preds = %for.body2021.i
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br label %for.end335.i
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while.end2742.i: ; preds = %while.body300.preheader.i
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br i1 undef, label %if.then2748.i, label %for.body2778.i
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if.then2748.i: ; preds = %while.end2742.i
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unreachable
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for.body2778.i: ; preds = %while.end2742.i
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unreachable
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for.inc27.us.5.i: ; preds = %if.end.i
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br label %for.end30.i
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if.end85: ; preds = %entry
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ret void
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}
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declare void @fprintf(...) nounwind
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