mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-24 05:23:45 +02:00
80e7bd96da
Summary:
This patch adds support for predicates on imm nodes but only for ImmLeaf and not
for PatLeaf or PatFrag and only where the value does not need to be transformed
before being rendered into the instruction.
The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the
necessary target-supplied C++ for GlobalISel.
Depends on D36085
The previous commit was reverted for breaking the build but this appears to have
been the recurring problem on the Windows bots with tablegen not being re-run
when llvm-tblgen is changed but the .td's aren't. If it re-occurs then forcing a
build with clean=True should fix it but this string should do this in advance:
Requires a clean build.
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: rovka
Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D36086
llvm-svn: 311645
38 lines
1.1 KiB
YAML
38 lines
1.1 KiB
YAML
# RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
|
|
|
|
--- |
|
|
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
|
|
|
define void @vcvtfxu2fp_s64_fpr() { ret void }
|
|
...
|
|
|
|
---
|
|
# Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
|
|
# CHECK-LABEL: name: vcvtfxu2fp_s64_fpr
|
|
name: vcvtfxu2fp_s64_fpr
|
|
legalized: true
|
|
regBankSelected: true
|
|
|
|
# CHECK: registers:
|
|
# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
|
|
# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' }
|
|
registers:
|
|
- { id: 0, class: fpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: fpr }
|
|
|
|
# CHECK: body:
|
|
# CHECK: %0 = COPY %d0
|
|
# CHECK: %2 = UCVTFd %0, 12
|
|
# CHECK: %d1 = COPY %2
|
|
body: |
|
|
bb.0:
|
|
liveins: %d0
|
|
|
|
%0(s64) = COPY %d0
|
|
%1(s32) = G_CONSTANT i32 12
|
|
%2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1
|
|
%d1 = COPY %2(s64)
|
|
...
|