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8758eb180c
We can infer this from the incoming MIR, so there's no reason to represent it with a special flag. llvm-svn: 304246
65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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define i32 @main() {
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entry:
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ret i32 0
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}
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declare i32 @printf(i8*, ...)
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...
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---
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# CHECK-LABEL: name: main
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name: main
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alignment: 2
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exposesReturnsTwice: false
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legalized: true
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regBankSelected: true
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gpr }
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- { id: 8, class: gpr }
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- { id: 9, class: gpr }
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- { id: 10, class: gpr }
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- { id: 11, class: gpr }
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- { id: 12, class: gpr }
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- { id: 13, class: gpr }
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- { id: 14, class: gpr }
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- { id: 15, class: gpr }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 8
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adjustsStack: false
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hasCalls: true
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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# CHECK: body:
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# CHECK: %1 = COPY %w0
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# CHECK-NOT: %2 = ORNWrr %wzr, %1
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# CHECK: %4 = EONWrr %1, %3
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body: |
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bb.1.entry:
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liveins: %w0
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%0(s32) = G_CONSTANT i32 -1
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%3(s32) = G_CONSTANT i32 1
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%1(s32) = COPY %w0
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%2(s32) = G_XOR %1, %0
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%4(s32) = G_XOR %2, %3
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%w0 = COPY %4(s32)
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...
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