1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 11:42:57 +01:00
llvm-mirror/test/MC/Mips/crc/invalid64.s
Petar Jovanovic 0510f66dad [mips] Add support for CRC ASE
This includes

  Instructions: crc32b, crc32h, crc32w, crc32d,
                crc32cb, crc32ch, crc32cw, crc32cd

  Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc

  Attribute: crc

  .MIPS.abiflags: CRC (0x8000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44176

llvm-svn: 327511
2018-03-14 14:13:31 +00:00

25 lines
1.6 KiB
ArmAsm

# Instructions that are invalid.
#
# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -mcpu=mips64r6 \
# RUN: -mattr=+crc 2>%t1
# RUN: FileCheck %s < %t1
.set noat
crc32d $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
crc32d $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
crc32d $1, $2, 2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
crc32d $1, 2, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
crc32d 1, $2, $2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
crc32d $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
crc32d $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
crc32d $1, $2, 0($2) # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
crc32cd $1, $2, $2 # CHECK: :[[@LINE]]:3: error: source and destination must match
crc32cd $1, $2, $3 # CHECK: :[[@LINE]]:3: error: source and destination must match
crc32cd $1, $2, 2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
crc32cd $1, 2, $2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
crc32cd 1, $2, $2 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
crc32cd $1, $2 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
crc32cd $1 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
crc32cd $1, $2, 0($2) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction