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143 lines
6.0 KiB
TableGen
143 lines
6.0 KiB
TableGen
// RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
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// RUN: -combiners=MyCombinerHelper -gicombiner-stop-after-build %s \
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// RUN: -o %t.inc | FileCheck %s
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include "llvm/Target/Target.td"
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include "llvm/Target/GlobalISel/Combine.td"
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def dummy;
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
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def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
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def SUB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
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def MUL : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
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def TRUNC : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
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def SEXT : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
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def ZEXT : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
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def Rule0 : GICombineRule<
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(defs root:$d),
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(match (MUL $t, $s1, $s2),
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(SUB $d, $t, $s3)),
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(apply [{ APPLY }])>;
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def Rule1 : GICombineRule<
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(defs root:$d),
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(match (MOV $s1, $s2),
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(MOV $d, $s1)),
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(apply [{ APPLY }])>;
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def Rule2 : GICombineRule<
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(defs root:$d),
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(match (MOV $d, $s)),
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(apply [{ APPLY }])>;
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def Rule3 : GICombineRule<
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(defs root:$d),
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(match (MUL $t, $s1, $s2),
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(ADD $d, $t, $s3), [{ A }]),
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(apply [{ APPLY }])>;
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def Rule4 : GICombineRule<
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(defs root:$d),
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(match (ADD $d, $s1, $s2)),
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(apply [{ APPLY }])>;
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def Rule5 : GICombineRule<
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(defs root:$d),
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(match (SUB $d, $s1, $s2)),
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(apply [{ APPLY }])>;
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def Rule6 : GICombineRule<
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(defs root:$d),
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(match (SEXT $t, $s1),
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(TRUNC $d, $t)),
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(apply [{ APPLY }])>;
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def Rule7 : GICombineRule<
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(defs root:$d),
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(match (ZEXT $t, $s1),
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(TRUNC $d, $t)),
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(apply [{ APPLY }])>;
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def MyCombinerHelper: GICombinerHelper<"GenMyCombinerHelper", [
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Rule0,
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Rule1,
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Rule2,
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Rule3,
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Rule4,
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Rule5,
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Rule6,
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Rule7
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]>;
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// CHECK-LABEL: digraph "matchtree" {
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// CHECK-DAG: Node[[N0:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[0].getOpcode()|4 partitions|Rule0,Rule1,Rule2,Rule3,Rule4,Rule5,Rule6,Rule7}"]
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// CHECK-DAG: Node[[N1:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1] = getVRegDef(MI[0].getOperand(1))|2 partitions|Rule0,Rule5}"]
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// CHECK-DAG: Node[[N2:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1].getOpcode()|2 partitions|Rule0,Rule5}"]
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// CHECK-DAG: Node[[N3:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule0}"]
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// CHECK-DAG: Node[[N4:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule5}"]
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// CHECK-DAG: Node[[N5:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule5}"]
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// CHECK-DAG: Node[[N6:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1] = getVRegDef(MI[0].getOperand(1))|2 partitions|Rule1,Rule2}"]
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// CHECK-DAG: Node[[N7:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1].getOpcode()|2 partitions|Rule1,Rule2}"]
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// CHECK-DAG: Node[[N8:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule1}"]
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// CHECK-DAG: Node[[N9:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule2}"]
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// CHECK-DAG: Node[[N10:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule2}"]
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// CHECK-DAG: Node[[N11:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1] = getVRegDef(MI[0].getOperand(1))|2 partitions|Rule3,Rule4}"]
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// CHECK-DAG: Node[[N12:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1].getOpcode()|2 partitions|Rule3,Rule4}"]
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// CHECK-DAG: Node[[N13:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule3,Rule4}",color=red]
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// CHECK-DAG: Node[[N14:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule4}"]
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// CHECK-DAG: Node[[N15:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule4}"]
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// CHECK-DAG: Node[[N16:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1] = getVRegDef(MI[0].getOperand(1))|1 partitions|Rule6,Rule7}"]
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// CHECK-DAG: Node[[N17:(0x)?[0-9a-fA-F]+]] [shape=record,label="{MI[1].getOpcode()|2 partitions|Rule6,Rule7}"]
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// CHECK-DAG: Node[[N18:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule6}"]
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// CHECK-DAG: Node[[N19:(0x)?[0-9a-fA-F]+]] [shape=record,label="{No partitioner|Rule7}"]
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// The most important partitioner is on the first opcode:
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// CHECK-DAG: Node[[N0]] -> Node[[N1]] [label="#0 MyTarget::SUB"]
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// CHECK-DAG: Node[[N0]] -> Node[[N6]] [label="#1 MyTarget::MOV"]
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// CHECK-DAG: Node[[N0]] -> Node[[N11]] [label="#2 MyTarget::ADD"]
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// CHECK-DAG: Node[[N0]] -> Node[[N16]] [label="#3 MyTarget::TRUNC"]
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// For, MI[0].getOpcode() == SUB, then has to determine whether it has a reg
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// operand and follow that link. If it can't then Rule5 is the only choice as
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// that rule is not constrained to a reg.
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// CHECK-DAG: Node[[N1]] -> Node[[N2]] [label="#0 true"]
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// CHECK-DAG: Node[[N1]] -> Node[[N5]] [label="#1 false"]
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// For, MI[0].getOpcode() == SUB && MI[0].getOperand(1).isReg(), if MI[1] is a
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// MUL then it must be either Rule0 or Rule5. Rule0 is fully tested so Rule5 is
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// unreachable. If it's not MUL then it must be Rule5.
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// CHECK-DAG: Node[[N2]] -> Node[[N3]] [label="#0 MyTarget::MUL"]
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// CHECK-DAG: Node[[N2]] -> Node[[N4]] [label="#1 * or nullptr"]
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// CHECK-DAG: Node[[N6]] -> Node[[N7]] [label="#0 true"]
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// CHECK-DAG: Node[[N6]] -> Node[[N10]] [label="#1 false"]
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// CHECK-DAG: Node[[N7]] -> Node[[N8]] [label="#0 MyTarget::MOV"]
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// CHECK-DAG: Node[[N7]] -> Node[[N9]] [label="#1 * or nullptr"]
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// CHECK-DAG: Node[[N11]] -> Node[[N12]] [label="#0 true"]
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// CHECK-DAG: Node[[N11]] -> Node[[N15]] [label="#1 false"]
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// CHECK-DAG: Node[[N12]] -> Node[[N13]] [label="#0 MyTarget::MUL"]
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// CHECK-DAG: Node[[N12]] -> Node[[N14]] [label="#1 * or nullptr"]
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// CHECK-DAG: Node[[N16]] -> Node[[N17]] [label="#0 true"]
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// CHECK-DAG: Node[[N17]] -> Node[[N18]] [label="#0 MyTarget::SEXT"]
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// CHECK-DAG: Node[[N17]] -> Node[[N19]] [label="#1 MyTarget::ZEXT"]
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// CHECK-LABEL: {{^}$}}
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