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342e72a308
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
166 lines
4.8 KiB
LLVM
166 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
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;FUNC-LABEL: {{^}}test1:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
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;SI-CHECK-NOT: [[REG]]
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;SI-CHECK: buffer_store_dword [[REG]],
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define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%a = load i32 addrspace(1)* %in
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%b = load i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}test2:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1)* %in
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%b = load <2 x i32> addrspace(1)* %b_ptr
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%result = add <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}test4:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1)* %in
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%b = load <4 x i32> addrspace(1)* %b_ptr
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%result = add <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test8:
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
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entry:
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%0 = add <8 x i32> %a, %b
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store <8 x i32> %0, <8 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test16:
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
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entry:
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%0 = add <16 x i32> %a, %b
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store <16 x i32> %0, <16 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}add64:
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; SI-CHECK: s_add_u32
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; SI-CHECK: s_addc_u32
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define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%0 = add i64 %a, %b
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
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; use VCC. The test is designed so that %a will be stored in an SGPR and
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; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
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; to a VGPR before doing the add.
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; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
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; SI-CHECK-NOT: v_addc_u32_e32 s
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define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64 addrspace(1)* %in
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%1 = add i64 %a, %0
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; Test i64 add inside a branch.
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; FUNC-LABEL: {{^}}add64_in_branch:
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; SI-CHECK: s_add_u32
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; SI-CHECK: s_addc_u32
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define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i64 addrspace(1)* %in
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br label %endif
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else:
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%2 = add i64 %a, %b
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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