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342fca5b08
Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
92 lines
4.2 KiB
TableGen
Executable File
92 lines
4.2 KiB
TableGen
Executable File
//===-- LeonFeatures.td - Describe the Leon Features -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699
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// We need to have the option to switch this on and off.
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//===----------------------------------------------------------------------===//
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// support to casa instruction; for leon3 subtarget only
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def LeonCASA : SubtargetFeature<
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"hasleoncasa", "HasLeonCasa", "true",
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"Enable CASA instruction for LEON3 and LEON4 processors">;
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//===----------------------------------------------------------------------===//
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// UMAC and SMAC support for LEON3 and LEON4 processors.
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//===----------------------------------------------------------------------===//
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// support to casa instruction; for leon3 subtarget only
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def UMACSMACSupport
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: SubtargetFeature<"hasumacsmac", "HasUmacSmac", "true",
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"Enable UMAC and SMAC for LEON3 and LEON4 processors">;
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//===----------------------------------------------------------------------===//
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// LEON Erratum fixes
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//===----------------------------------------------------------------------===//
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def ReplaceSDIV
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: SubtargetFeature<
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"replacesdiv", "PerformSDIVReplace", "true",
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"AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead">;
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def FixCALL
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: SubtargetFeature<"fixcall", "FixCallImmediates", "true",
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"AT697E erratum fix: Restrict the size of the immediate "
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"operand of the CALL instruction to 20 bits">;
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def IgnoreZeroFlag
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: SubtargetFeature<"ignrzeroflag", "IgnoreZeroFlag", "true",
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"AT697E erratum fix: Do not rely on the zero bit flag "
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"on a divide overflow for SDIVCC and UDIVCC">;
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def InsertNOPDoublePrecision
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: SubtargetFeature<"insrtnopdblprcsn", "InsertNOPDoublePrecision", "true",
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"LEON2 erratum fix: Insert a NOP before the double "
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"precision floating point instruction">;
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def FixFSMULD : SubtargetFeature<"fixfsmuld", "FixFSMULD", "true",
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"LEON3 erratum fix: Do not select FSMULD">;
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def ReplaceFMULS
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: SubtargetFeature<"replacefmuls", "ReplaceFMULS", "true",
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"LEON3 erratum fix: Replace FMULS instruction with a "
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"routine using conversions/double precision operations "
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"to replace FMULS">;
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def PreventRoundChange
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: SubtargetFeature<"prvntroundchange", "PreventRoundChange", "true",
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"LEON3 erratum fix: Prevent any rounding mode change "
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"request: use only the round-to-nearest rounding mode">;
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def FixAllFDIVSQRT
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: SubtargetFeature<"fixallfdivsqrt", "FixAllFDIVSQRT", "true",
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"LEON3 erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD "
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"instructions with NOPs and floating-point store">;
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def InsertNOPLoad
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: SubtargetFeature<"insertnopload", "InsertNOPLoad", "true",
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"LEON3 erratum fix: Insert a NOP instruction after "
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"every single-cycle load instruction when the next "
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"instruction is another load/store instruction">;
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def FlushCacheLineSWAP
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: SubtargetFeature<"flshcachelineswap", "FlushCacheLineSWAP", "true",
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"LEON3 erratum fix: Flush cache line containing the "
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"lock before performing any of the atomic instructions "
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"SWAP and LDSTUB">;
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def InsertNOPsLoadStore
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: SubtargetFeature<"insertnopsloadstore", "InsertNOPsLoadStore", "true",
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"LEON3 erratum fix: Insert NOPs between "
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"single-precision loads and the store, so the number of "
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"instructions between is 4">;
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