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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
llvm-mirror/test/CodeGen/AMDGPU
Ruiling Song 236d926c95 [AMDGPU] Update LiveVariables in convertToThreeAddress()
This can fix an asan failure like below.
==15856==ERROR: AddressSanitizer: use-after-poison on address ...
READ of size 8 at 0x6210001a3cb0 thread T0
    #0 llvm::MachineInstr::getParent()
    #1 llvm::LiveVariables::VarInfo::findKill()
    #2 TwoAddressInstructionPass::rescheduleMIBelowKill()
    #3 TwoAddressInstructionPass::tryInstructionTransform()
    #4 TwoAddressInstructionPass::runOnMachineFunction()

We need to update the Kills if we replace instructions. The Kills
may be later accessed within TwoAddressInstruction pass.

Differential Revision: https://reviews.llvm.org/D89092
2020-10-13 08:12:20 +08:00
..
GlobalISel [AMDGPU] Only enable mad/mac legacy f32 patterns if denormals may be flushed 2020-10-09 17:08:38 +01:00
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directive-amdgcn-target.ll [AMDGPU] Add gfx602, gfx705, gfx805 targets 2020-10-10 17:22:22 +01:00
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elf-header-flags-mach.ll [AMDGPU] Add gfx602, gfx705, gfx805 targets 2020-10-10 17:22:22 +01:00
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hsa-metadata-wavefrontsize.ll
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i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
i1-copy-phi.ll
i8-to-double-to-float.ll
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icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll
idot2.ll
idot4s.ll
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idot8s.ll
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illegal-sgpr-to-vgpr-copy.ll
image_ls_mipmap_zero.ll
image-attributes.ll
image-load-d16-tfe.ll
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image-sample-waterfall.ll
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imm16.ll
imm.ll
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implicit-def-muse.ll
indirect-addressing-si-gfx9.ll
indirect-addressing-si-noopt.ll
indirect-addressing-si-pregfx9.ll
indirect-addressing-si.ll
indirect-addressing-term.ll
indirect-call.ll [AMDGPU] Insert waterfall loops for divergent calls 2020-10-12 17:16:11 +02:00
indirect-private-64.ll
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input-mods.ll
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llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.append.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll
llvm.amdgcn.ds.gws.barrier.ll
llvm.amdgcn.ds.gws.init.ll
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llvm.amdgcn.ds.gws.sema.release.all.ll
llvm.amdgcn.ds.gws.sema.v.ll
llvm.amdgcn.ds.ordered.add.gfx10.ll
llvm.amdgcn.ds.ordered.add.ll
llvm.amdgcn.ds.ordered.swap.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.exp.prim.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
llvm.amdgcn.fmad.ftz.f16.ll
llvm.amdgcn.fmad.ftz.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll [AMDGPU] Only enable mad/mac legacy f32 patterns if denormals may be flushed 2020-10-09 17:08:38 +01:00
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.a16.dim.ll
llvm.amdgcn.image.a16.encode.ll
llvm.amdgcn.image.atomic.dim.ll
llvm.amdgcn.image.d16.dim.ll
llvm.amdgcn.image.dim.ll
llvm.amdgcn.image.gather4.a16.dim.ll
llvm.amdgcn.image.gather4.d16.dim.ll
llvm.amdgcn.image.gather4.dim.ll
llvm.amdgcn.image.gather4.o.dim.ll
llvm.amdgcn.image.getlod.dim.ll
llvm.amdgcn.image.load.a16.d16.ll
llvm.amdgcn.image.load.a16.ll
llvm.amdgcn.image.msaa.load.ll
llvm.amdgcn.image.nsa.ll
llvm.amdgcn.image.sample.a16.dim.ll
llvm.amdgcn.image.sample.d16.dim.ll
llvm.amdgcn.image.sample.dim.ll
llvm.amdgcn.image.sample.g16.encode.ll
llvm.amdgcn.image.sample.g16.ll
llvm.amdgcn.image.sample.ltolz.ll
llvm.amdgcn.image.sample.o.dim.ll
llvm.amdgcn.image.store.a16.d16.ll
llvm.amdgcn.image.store.a16.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
llvm.amdgcn.init.exec.ll
llvm.amdgcn.init.exec.wave32.ll
llvm.amdgcn.interp.f16.ll
llvm.amdgcn.interp.ll
llvm.amdgcn.intersect_ray.ll
llvm.amdgcn.is.private.ll
llvm.amdgcn.is.shared.ll
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.ll
llvm.amdgcn.mov.dpp8.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
llvm.amdgcn.mul.u24.ll
llvm.amdgcn.permlane.ll
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.raw.buffer.atomic.fadd.ll
llvm.amdgcn.raw.buffer.atomic.ll
llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm.amdgcn.raw.buffer.load.format.ll
llvm.amdgcn.raw.buffer.load.ll
llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm.amdgcn.raw.tbuffer.load.ll
llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm.amdgcn.raw.tbuffer.store.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.buffer.load.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.setreg.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
llvm.amdgcn.sdot4.ll
llvm.amdgcn.sdot8.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll
llvm.amdgcn.sqrt.f16.ll
llvm.amdgcn.sqrt.ll
llvm.amdgcn.struct.buffer.atomic.fadd.ll
llvm.amdgcn.struct.buffer.atomic.ll
llvm.amdgcn.struct.buffer.load.format.d16.ll
llvm.amdgcn.struct.buffer.load.format.ll
llvm.amdgcn.struct.buffer.load.ll
llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm.amdgcn.struct.buffer.store.format.ll
llvm.amdgcn.struct.buffer.store.ll
llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm.amdgcn.struct.tbuffer.load.ll
llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm.amdgcn.struct.tbuffer.store.ll
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.udot2.ll
llvm.amdgcn.udot4.ll
llvm.amdgcn.udot8.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
llvm.ceil.f16.ll
llvm.cos.f16.ll
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
llvm.fmuladd.f16.ll
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
llvm.log10.ll
llvm.log.f16.ll
llvm.log.ll
llvm.maxnum.f16.ll
llvm.memcpy.ll
llvm.minnum.f16.ll
llvm.mulo.ll
llvm.pow.ll
llvm.powi.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
lo16-32bit-physreg-copy.mir
lo16-hi16-illegal-copy.mir
lo16-hi16-physreg-copy.mir
lo16-lo16-physreg-copy-agpr.mir
lo16-lo16-physreg-copy-sgpr.mir
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i8.ll
load-local-i16.ll
load-local-i32.ll
load-local-i64.ll
load-local-redundant-copies.ll
load-local.96.ll
load-local.128.ll
load-select-ptr.ll
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics-fp.ll
local-atomics.ll
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-alloc-block-sp-reference.ll
local-stack-slot-offset.ll
loop_break.ll
loop_exit_with_xor.ll
loop_header_nopred.mir
loop-address.ll
loop-idiom.ll
loop-prefetch.ll
lower-control-flow-other-terminators.mir
lower-kernargs.ll
lower-mem-intrinsics-threshold.ll
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll
machine-cse-commute-target-flags.mir
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll
mad-mix.ll
mad.u16.ll
madak-inline-constant.mir
madak.ll
madmk.ll
mai-hazards.mir [AMDGPU] Fix mai hazard VALU to LD/ST 2020-10-08 17:13:02 -07:00
mai-inline.ll
max3.ll
max-literals.ll
max-sgprs.ll
max.i16.ll
max.ll
mcp-overlap-after-propagation.mir
med3-no-simplify.ll
mem-builtins.ll
memcpy-fixed-align.ll
memcpy-inline-fails.ll
memory_clause.ll
memory_clause.mir
memory-legalizer-amdpal.ll
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-insert-end.mir
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-addrspace.mir
memory-legalizer-invalid-syncscope.ll
memory-legalizer-load.ll
memory-legalizer-local.mir
memory-legalizer-mesa3d.ll
memory-legalizer-multiple-mem-operands-atomics.mir
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
memory-legalizer-region.mir
memory-legalizer-store-infinite-loop.ll
memory-legalizer-store.ll
merge-image-load-gfx10.mir
merge-image-load.mir
merge-image-sample-gfx10.mir
merge-image-sample.mir
merge-load-store-physreg.mir
merge-load-store-vreg.mir
merge-load-store.mir
merge-m0.mir
merge-out-of-order-ldst.ll
merge-out-of-order-ldst.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
merge-tbuffer.mir
mesa3d.ll
mesa_regression.ll
mfma-loop.ll
min3.ll
min.ll
mir-print-dead-csr-fi.mir
misched-killflags.mir
missing-store.ll
mixed_wave32_wave64.ll
mixed-wave32-wave64.ll
mode-register.mir
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
mubuf-legalize-operands.mir
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul24-pass-ordering.ll
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
mul.i16.ll
mul.ll
multi-divergent-exit-region.ll
multi-dword-vgpr-spill.ll
multilevel-break.ll
nand.ll
nested-calls.ll
nested-loop-conditions.ll
no-bundle-asm.ll
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-remat-indirect-mov.mir
no-shrink-extloads.ll
non-entry-alloca.ll
noop-shader-O0.ll
nop-data.ll
nop-fold.mir
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll
nsa-vmem-hazard.mir
nullptr.ll
occupancy-levels.ll
offset-split-flat.ll
offset-split-global.ll
omod-nsz-flag.mir
omod.ll
opencl-image-metadata.ll
opencl-printf-no-hostcall.ll
opencl-printf.ll
operand-folding.ll
operand-spacing.ll
opt-pipeline.ll
opt-sgpr-to-vgpr-copy.mir
optimize-exec-copies-extra-insts-after-copy.mir
optimize-exec-mask-pre-ra-loop-phi.mir
optimize-exec-masking-pre-ra.mir
optimize-exec-masking-strip-terminator-bits.mir
optimize-if-exec-masking.mir
optimize-negated-cond-exec-masking-wave32.mir
optimize-negated-cond-exec-masking.mir
optimize-negated-cond.ll
or3.ll
or.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
pal-userdata-regs.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-reg-scavenger-position.mir
pei-scavenge-sgpr-carry-out.mir
pei-scavenge-sgpr-gfx9.mir
pei-scavenge-sgpr.mir
pei-scavenge-vgpr-spill.mir
perfhint.ll
permute.ll
phi-elimination-assertion.mir
phi-elimination-end-cf.mir
phi-vgpr-input-moveimm.mir
pk_max_f16_literal.ll
post-ra-sched-kill-bundle-use-inst.mir
postra-bundle-memops.mir
postra-machine-sink.mir
postra-norename.mir
power-sched-no-instr-sunit.mir
predicate-dp4.ll
predicates.ll
preserve-hi16.ll
print-mir-custom-pseudo.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll
promote-alloca-pointer-array.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-constantexpr-use.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
promote-alloca-volatile.ll
promote-constOffset-to-imm-gfx10.mir
promote-constOffset-to-imm.ll
promote-constOffset-to-imm.mir
propagate-attributes-bitcast-function.ll
propagate-attributes-clone.ll
propagate-attributes-single-set.ll
ptrmask.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
readlane_exec0.mir
README
reassoc-scalar.ll
reduce-build-vec-ext-to-ext-build-vec.ll
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
reg-coalescer-sched-crash.ll
regbank-reassign-wave64.mir
regbank-reassign.mir
regcoal-subrange-join-seg.mir
regcoal-subrange-join.mir
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
register-count-comments.ll
rel32.ll
remove-short-exec-branches-gpr-idx-mode.mir
remove-short-exec-branches-mode-def.mir
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll
reserve-vgpr-for-sgpr-spill.ll
ret_jump.ll
ret.ll
returnaddress.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_add_co_pseudo_lowering.mir
s_addk_i32.ll
s_code_end.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
saddo.ll
saddsat.ll
salu-to-valu.ll
sampler-resource-id.ll
scalar_to_vector_v2x16.ll
scalar_to_vector.ll
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
sched-assert-dead-def-subreg-use-other-subreg.mir
sched-assert-onlydbg-value-empty-region.mir
sched-crash-dbg-value.mir
sched-handleMoveUp-subreg-def-across-subreg-def.mir
sched-prefer-non-mfma.mir
schedule-barrier-fpmode.mir
schedule-barrier.mir
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
schedule-regpressure-limit3.ll
schedule-regpressure-limit-clustering.ll
schedule-regpressure-limit.ll
schedule-regpressure.mir
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
schedule-xdl-resource.ll
scheduler-handle-move-bundle.mir
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
sdiv64.ll
sdiv.ll
sdivrem24.ll
sdivrem64.r600.ll
sdwa-gfx9.mir
sdwa-op64-test.ll
sdwa-ops.mir
sdwa-peephole-instr-gfx10.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll
sdwa-preserve.mir
sdwa-scalar-ops.mir
sdwa-stack.mir
sdwa-vop2-64bit.mir
select64.ll
select-constant-cttz.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
select-i1.ll
select-opt.ll
select-undef.ll
select-vectors.ll
select.f16.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
set-gpr-idx-peephole.mir
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
setcc-opt.ll
setcc-sext.ll
setcc.ll
seto.ll
setuo.ll
sext-divergence-driven-isel.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
sgpr-control-flow.ll
sgpr-copy-duplicate-operand.ll
sgpr-copy-local-cse.ll
sgpr-copy.ll
sgpr-spill-partially-undef.mir
sgpr-spill-wrong-stack-id.mir
sgpr-spill.mir
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll
shift-select.ll
shl_add_constant.ll
shl_add_ptr_csub.ll
shl_add_ptr_global.ll
shl_add_ptr.ll
shl_add.ll
shl_or.ll
shl-add-to-add-shl.ll
shl.ll
shl.v2i16.ll
shrink-add-sub-constant.ll
shrink-carry.mir
shrink-instructions-flags.mir
shrink-instructions-implicit-vcclo.mir
shrink-insts-scalar-bit-ops.mir
shrink-vop3-carry-out.mir
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
si-annotate-cf.ll
si-annotate-cfg-loop-assert.ll
si-annotatecfg-multiple-backedges.ll
si-fix-sgpr-copies.mir
si-i1-copies.mir
si-instr-info-correct-implicit-operands.ll
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
si-lower-i1-copies.mir
si-lower-sgpr-spills.mir
si-scheduler.ll
si-sgpr-spill.ll
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll
sign_extend.ll
simplify-libcalls2.ll
simplify-libcalls.ll
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
sint_to_fp.ll
sitofp.f16.ll
skip-branch-taildup-ret.mir
skip-branch-trap.ll
skip-if-dead.ll
smed3.ll
smem-no-clause-coalesced.mir
smem-war-hazard.mir
sminmax.ll
sminmax.v2i16.ll
smrd_vmem_war.ll
smrd-fold-offset.mir
smrd-gfx10.ll
smrd-vccz-bug.ll
smrd.ll
sopk-compares.ll
speculative-execution-freecasts.ll
spill192.mir
spill_more_than_wavesize_csr_sgprs.ll
spill-agpr.ll
spill-agpr.mir
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir
spill-cfg-position.ll
spill-csr-frame-ptr-reg-copy.ll
spill-empty-live-interval.mir
spill-m0.ll
spill-offset-calculation.ll
spill-reg-tuple-super-reg-use.mir
spill-scavenge-offset.ll
spill-special-sgpr.mir
spill-vgpr-to-agpr.ll
spill-wide-sgpr.ll
split-arg-dbg-value.ll
split-scalar-i64-add.ll
split-smrd.ll
split-vector-memoperand-offsets.ll
splitkit-copy-bundle.mir
splitkit-copy-live-lanes.mir
splitkit-getsubrangeformask.ll
splitkit-nolivesubranges.mir
splitkit.mir
sra.ll
sram-ecc-default.ll
srem64.ll
srem.ll
srl.ll
sroa-before-unroll.ll
SRSRC-GIT-clobber-check.mir
ssubo.ll
ssubsat.ll
stack-pointer-offset-relative-frameindex.ll
stack-realign-kernel.ll
stack-realign.ll
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
stale-livevar-in-twoaddr-pass.mir [AMDGPU] Update LiveVariables in convertToThreeAddress() 2020-10-13 08:12:20 +08:00
store_typed.ll
store-barrier.ll
store-global.ll
store-hi16.ll
store-local.96.ll
store-local.128.ll
store-local.ll
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll
stress-calls.ll
strict_fadd.f16.ll
strict_fadd.f32.ll
strict_fadd.f64.ll
strict_fma.f16.ll
strict_fma.f32.ll
strict_fma.f64.ll
strict_fmul.f16.ll
strict_fmul.f32.ll
strict_fmul.f64.ll
strict_fsub.f16.ll
strict_fsub.f32.ll
strict_fsub.f64.ll
structurize1.ll
structurize.ll
sub_i1.ll
sub-zext-cc-zext-cc.ll
sub.i16.ll
sub.ll
sub.v2i16.ll
subreg_interference.mir
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir
subreg-undef-def-with-other-subreg-defs.mir
subvector-test.mir
switch-default-block-unreachable.ll
switch-unreachable.ll
swizzle-export.ll
syncscopes.ll
tail-call-cgp.ll
tail-dup-bundle.mir
tail-duplication-convergent.ll
target-cpu.ll
tex-clause-antidep.ll
texture-input-merge.ll
token-factor-inline-limit-test.ll
transform-block-with-return-to-epilog.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store-i64.ll
trunc-store-vec-i16-to-i8.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll
tti-unroll-prefs.ll
twoaddr-fma.mir
twoaddr-mad.mir
uaddo.ll
uaddsat.ll
udiv64.ll
udiv.ll
udivrem24.ll
udivrem64.r600.ll
udivrem.ll
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
uitofp.f16.ll
umed3.ll
unaligned-load-store.ll
undefined-physreg-sgpr-spill.mir
undefined-subreg-liverange.ll
unexpected-reg-unit-state.mir
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
uniform-work-group-attribute-missing.ll
uniform-work-group-nested-function-calls.ll
uniform-work-group-prevent-attribute-propagation.ll
uniform-work-group-propagate-attribute.ll
uniform-work-group-recursion-test.ll
uniform-work-group-test.ll
unify-metadata.ll
unigine-liveness-crash.ll
unknown-processor.ll
unpack-half.ll
unroll.ll
unsupported-calls.ll
unsupported-cc.ll
unsupported-image-a16.ll
unsupported-image-g16.ll
update-phi.ll
urem64.ll
urem.ll
use-sgpr-multiple-times.ll
usubo.ll
usubsat.ll
v1i64-kernel-arg.ll
v1024.ll
v_cndmask.ll
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
v_mac.ll
v_madak_f16.ll
v_swap_b32.mir
valu-i1.ll
vccz-corrupt-bug-workaround.mir
vcmpx-exec-war-hazard.mir
vcmpx-permlane-hazard.mir
vector_shuffle.packed.ll
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca-bitcast.ll
vector-alloca-limits.ll
vector-alloca.ll
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-buffer-fat-pointer.ll
vectorize-global-local.ll
vectorize-loads.ll
verify-constant-bus-violations.mir
verify-sop.mir
vertex-fetch-encoding.ll
vgpr-descriptor-waterfall-loop-idom-update.ll
vgpr-spill-emergency-stack-slot-compute.ll
vgpr-spill-emergency-stack-slot.ll
vgpr-tuple-allocation.ll
vi-removed-intrinsics.ll
virtregrewrite-undef-identity-copy.mir
visit-physreg-vgpr-imm-folding-bug.ll
vmem-to-salu-hazard.mir
vmem-vcc-hazard.mir
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
waitcnt-back-edge-loop.mir
waitcnt-debug.mir
waitcnt-flat.ll
waitcnt-loop-irreducible.mir
waitcnt-loop-single-basic-block.mir
waitcnt-looptest.ll
waitcnt-meta-instructions.mir
waitcnt-no-redundant.mir
waitcnt-overflow.mir
waitcnt-permute.mir
waitcnt-preexisting.mir
waitcnt-skip-meta.mir
waitcnt-vmem-waw.mir
waitcnt-vscnt.ll
waitcnt-vscnt.mir
waitcnt.mir
wave32.ll
wave_dispatch_regs.ll
widen_extending_scalar_loads.ll
widen-smrd-loads.ll
widen-vselect-and-mask.ll
wqm.ll
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
wwm-reserved.ll
xfail.r600.bitcast.ll
xnor.ll
xor3-i1-const.ll
xor3.ll
xor_add.ll
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.