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llvm-mirror/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll
Matt Arsenault 8f74f32e3e AMDGPU: Add 24-bit mul intrinsics
Insert these during codegenprepare.

This works around a DAG issue where generic combines eliminate the and
asserting the high bits are zero, which then exposes an unknown read
source to the mul combine. It doesn't worth the hassle of trying to
insert an AssertZext or something to try to deal with it.

llvm-svn: 366094
2019-07-15 17:50:31 +00:00

15 lines
476 B
LLVM

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_mul_u24:
; GCN: v_mul_u32_u24
define amdgpu_kernel void @test_mul_u24(i32 addrspace(1)* %out, i32 %src1, i32 %src2) #1 {
%val = call i32 @llvm.amdgcn.mul.u24(i32 %src1, i32 %src2) #0
store i32 %val, i32 addrspace(1)* %out
ret void
}
declare i32 @llvm.amdgcn.mul.u24(i32, i32) #0
attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind }