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https://github.com/RPCS3/llvm-mirror.git
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a70016c8d5
Add the scratch wave offset to the scratch buffer descriptor (SRSrc) in the entry function prologue. This allows us to removes the scratch wave offset register from the calling convention ABI. As part of this change, allow the use of an inline constant zero for the SOffset of MUBUF instructions accessing the stack in entry functions when a frame pointer is not requested/required. Entry functions with calls still need to set up the calling convention ABI stack pointer register, and reference it in order to address arguments of called functions. The ABI stack pointer register remains unswizzled, but is now wave-relative instead of queue-relative. Non-entry functions also use an inline constant zero SOffset for wave-relative scratch access, but continue to use the stack and frame pointers as before. When the stack or frame pointer is converted to a swizzled offset it is now scaled directly, as the scratch wave offset no longer needs to be subtracted first. Update llvm/docs/AMDGPUUsage.rst to reflect these changes to the calling convention. Tags: #llvm Differential Revision: https://reviews.llvm.org/D75138
47 lines
2.1 KiB
YAML
47 lines
2.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck %s
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# The wrong form of scavengeRegister was used, so it wasn't accounting
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# for the iterator passed to eliminateFrameIndex. It was instead using
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# the current iterator in the scavenger, which was not yet set if the
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# spill was the first instruction in the block.
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---
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name: scavenge_register_position
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tracksRegLiveness: true
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# Force a frame larger than the immediate field with a large alignment.
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stack:
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- { id: 0, type: default, offset: 4096, size: 4, alignment: 8192 }
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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argumentInfo:
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privateSegmentWaveByteOffset: { reg: '$sgpr4' }
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body: |
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; CHECK-LABEL: name: scavenge_register_position
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
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; CHECK: $sgpr0 = S_ADD_U32 $sgpr0, $sgpr4, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr5 = S_MOV_B32 524288
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; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5)
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; CHECK: S_BRANCH %bb.1
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; CHECK: bb.1:
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr4 = S_MOV_B32 524288
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; CHECK: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, align 8192, addrspace 5)
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; CHECK: S_ENDPGM 0, implicit $vgpr0
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bb.0:
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$vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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S_BRANCH %bb.1
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bb.1:
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$vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
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S_ENDPGM 0, implicit $vgpr0
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...
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