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43dbbcf721
expressions. Also "fix" the longstanding bug where the computed size depends on the order of the visitation. We could try to predict the allocation order used by legalization, but it would never be 100% perfect. Until we start fixing the addresses somehow (or have a more reliable allocation scheme later), just try to compute the size based on the worst case padding.
166 lines
8.4 KiB
LLVM
166 lines
8.4 KiB
LLVM
; RUN: opt -S -disable-promote-alloca-to-vector -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s
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; RUN: llc -disable-promote-alloca-to-vector -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=ASM %s
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target datalayout = "A5"
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@all_lds = internal unnamed_addr addrspace(3) global [16384 x i32] undef, align 4
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@some_lds = internal unnamed_addr addrspace(3) global [32 x i32] undef, align 4
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@initializer_user_some = addrspace(1) global i32 ptrtoint ([32 x i32] addrspace(3)* @some_lds to i32), align 4
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@initializer_user_all = addrspace(1) global i32 ptrtoint ([16384 x i32] addrspace(3)* @all_lds to i32), align 4
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; This function cannot promote to using LDS because of the size of the
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; constant expression use in the function, which was previously not
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; detected.
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; IR-LABEL: @constant_expression_uses_all_lds(
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; IR: alloca
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; ASM-LABEL: constant_expression_uses_all_lds:
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; ASM: .amdhsa_group_segment_fixed_size 65536
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define amdgpu_kernel void @constant_expression_uses_all_lds(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
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entry:
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%stack = alloca [4 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 0
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 2
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%gep3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 3
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store i32 9, i32 addrspace(5)* %gep0
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store i32 10, i32 addrspace(5)* %gep1
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store i32 99, i32 addrspace(5)* %gep2
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store i32 43, i32 addrspace(5)* %gep3
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %idx
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%load = load i32, i32 addrspace(5)* %arrayidx, align 4
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store i32 %load, i32 addrspace(1)* %out
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store volatile i32 ptrtoint ([16384 x i32] addrspace(3)* @all_lds to i32), i32 addrspace(1)* undef
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ret void
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}
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; Has a constant expression use through a single level of constant
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; expression, but not enough LDS to block promotion
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; IR-LABEL: @constant_expression_uses_some_lds(
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; IR-NOT: alloca
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; ASM-LABEL: {{^}}constant_expression_uses_some_lds:
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; ASM: .amdhsa_group_segment_fixed_size 4224{{$}}
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define amdgpu_kernel void @constant_expression_uses_some_lds(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
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entry:
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%stack = alloca [4 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 0
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 2
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%gep3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 3
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store i32 9, i32 addrspace(5)* %gep0
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store i32 10, i32 addrspace(5)* %gep1
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store i32 99, i32 addrspace(5)* %gep2
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store i32 43, i32 addrspace(5)* %gep3
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %idx
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%load = load i32, i32 addrspace(5)* %arrayidx, align 4
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store i32 %load, i32 addrspace(1)* %out
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store volatile i32 ptrtoint ([32 x i32] addrspace(3)* @some_lds to i32), i32 addrspace(1)* undef
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ret void
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}
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declare void @callee(i8*)
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; IR-LABEL: @constant_expression_uses_all_lds_multi_level(
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; IR: alloca
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; ASM-LABEL: {{^}}constant_expression_uses_all_lds_multi_level:
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; ASM: .amdhsa_group_segment_fixed_size 65536{{$}}
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define amdgpu_kernel void @constant_expression_uses_all_lds_multi_level(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
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entry:
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%stack = alloca [4 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 0
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 2
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%gep3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 3
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store i32 9, i32 addrspace(5)* %gep0
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store i32 10, i32 addrspace(5)* %gep1
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store i32 99, i32 addrspace(5)* %gep2
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store i32 43, i32 addrspace(5)* %gep3
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %idx
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%load = load i32, i32 addrspace(5)* %arrayidx, align 4
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store i32 %load, i32 addrspace(1)* %out
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call void @callee(i8* addrspacecast (i8 addrspace(3)* bitcast (i32 addrspace(3)* getelementptr inbounds ([16384 x i32], [16384 x i32] addrspace(3)* @all_lds, i32 0, i32 8) to i8 addrspace(3)*) to i8*))
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ret void
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}
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; IR-LABEL: @constant_expression_uses_some_lds_multi_level(
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; IR-NOT: alloca
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; IR: llvm.amdgcn.workitem.id
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; ASM-LABEL: {{^}}constant_expression_uses_some_lds_multi_level:
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; ASM: .amdhsa_group_segment_fixed_size 4224{{$}}
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define amdgpu_kernel void @constant_expression_uses_some_lds_multi_level(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
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entry:
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%stack = alloca [4 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 0
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 2
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%gep3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 3
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store i32 9, i32 addrspace(5)* %gep0
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store i32 10, i32 addrspace(5)* %gep1
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store i32 99, i32 addrspace(5)* %gep2
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store i32 43, i32 addrspace(5)* %gep3
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %idx
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%load = load i32, i32 addrspace(5)* %arrayidx, align 4
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store i32 %load, i32 addrspace(1)* %out
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call void @callee(i8* addrspacecast (i8 addrspace(3)* bitcast (i32 addrspace(3)* getelementptr inbounds ([32 x i32], [32 x i32] addrspace(3)* @some_lds, i32 0, i32 8) to i8 addrspace(3)*) to i8*))
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ret void
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}
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; IR-LABEL: @constant_expression_uses_some_lds_global_initializer(
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; IR-NOT: alloca
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; IR: llvm.amdgcn.workitem.id
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; ASM-LABEL: {{^}}constant_expression_uses_some_lds_global_initializer:
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; ASM: .amdhsa_group_segment_fixed_size 4096{{$}}
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define amdgpu_kernel void @constant_expression_uses_some_lds_global_initializer(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
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entry:
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%stack = alloca [4 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 0
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 2
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%gep3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 3
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store i32 9, i32 addrspace(5)* %gep0
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store i32 10, i32 addrspace(5)* %gep1
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store i32 99, i32 addrspace(5)* %gep2
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store i32 43, i32 addrspace(5)* %gep3
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %idx
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%load = load i32, i32 addrspace(5)* %arrayidx, align 4
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store i32 %load, i32 addrspace(1)* %out
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store volatile i32 ptrtoint (i32 addrspace(1)* @initializer_user_some to i32), i32 addrspace(1)* undef
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ret void
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}
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; We can't actually handle LDS initializers in global initializers,
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; but this should count as usage.
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; IR-LABEL: @constant_expression_uses_all_lds_global_initializer(
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; IR: alloca
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; ASM-LABEL: {{^}}constant_expression_uses_all_lds_global_initializer:
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; ASM: .group_segment_fixed_size: 65536
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define amdgpu_kernel void @constant_expression_uses_all_lds_global_initializer(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
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entry:
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%stack = alloca [4 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 0
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 2
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%gep3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 3
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store i32 9, i32 addrspace(5)* %gep0
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store i32 10, i32 addrspace(5)* %gep1
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store i32 99, i32 addrspace(5)* %gep2
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store i32 43, i32 addrspace(5)* %gep3
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %stack, i32 0, i32 %idx
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%load = load i32, i32 addrspace(5)* %arrayidx, align 4
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store i32 %load, i32 addrspace(1)* %out
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store volatile i32 ptrtoint (i32 addrspace(1)* @initializer_user_all to i32), i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { "amdgpu-waves-per-eu"="1,5" "amdgpu-flat-work-group-size"="256,256" }
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