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8553d88165
The AMDGPU target has a convention that defined all VGPRs (execept the initial 32 argument registers) as callee-saved. This convention is not efficient always, esp. when the callee requiring more registers, ended up emitting a large number of spills, even though its caller requires only a few. This patch revises the ABI by introducing more scratch registers that a callee can freely use. The 256 vgpr registers now become: 32 argument registers 112 scratch registers and 112 callee saved registers. The scratch registers and the CSRs are intermixed at regular intervals (a split boundary of 8) to obtain a better occupancy. Reviewers: arsenm, t-tye, rampitec, b-sumner, mjbedy, tpr Reviewed By: arsenm, t-tye Differential Revision: https://reviews.llvm.org/D76356
33 lines
1.0 KiB
LLVM
33 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=1 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}spill_csr_s5_copy:
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; GCN: s_or_saveexec_b64
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; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec
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; GCN: v_writelane_b32 v40, s33, 2
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; GCN: s_swappc_b64
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; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 9
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; GCN: buffer_store_dword [[K]], off, s[0:3], s33{{$}}
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; GCN: v_readlane_b32 s33, v40, 2
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; GCN: s_or_saveexec_b64
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; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
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; GCN: s_mov_b64 exec
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; GCN: s_setpc_b64
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define void @spill_csr_s5_copy() #0 {
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bb:
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%alloca = alloca i32, addrspace(5)
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%tmp = tail call i64 @func() #1
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* null, i64 %tmp
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%tmp2 = load i32, i32 addrspace(1)* %tmp1, align 4
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%tmp3 = zext i32 %tmp2 to i64
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store volatile i32 9, i32 addrspace(5)* %alloca
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ret void
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}
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declare i64 @func()
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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