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3529c0cbe0
These correspond to IMAGE_ATOMIC_* and are going to be used by Mesa for the GL_ARB_shader_image_load_store extension. Initial change by Nicolai H.hnle Differential Revision: http://reviews.llvm.org/D17401 llvm-svn: 262701
305 lines
9.9 KiB
TableGen
305 lines
9.9 KiB
TableGen
//===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the R600-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUReadPreloadRegisterIntrinsic<string name>
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<name>;
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let TargetPrefix = "r600" in {
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multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz<string prefix> {
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def _x : AMDGPUReadPreloadRegisterIntrinsic<!strconcat(prefix, "_x")>;
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def _y : AMDGPUReadPreloadRegisterIntrinsic<!strconcat(prefix, "_y")>;
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def _z : AMDGPUReadPreloadRegisterIntrinsic<!strconcat(prefix, "_z")>;
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}
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defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_global_size">;
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defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_local_size">;
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defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_ngroups">;
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defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_tgid">;
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defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_tidig">;
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def int_r600_rat_store_typed :
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// 1st parameter: Data
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// 2nd parameter: Index
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// 3rd parameter: Constant RAT ID
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Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
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GCCBuiltin<"__builtin_r600_rat_store_typed">;
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def int_r600_rsq : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_r600_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <
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"__builtin_r600_read_workdim"
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>;
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} // End TargetPrefix = "r600"
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// FIXME: These should be renamed/moved to r600
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let TargetPrefix = "AMDGPU" in {
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def int_AMDGPU_ldexp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
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>;
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}
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let TargetPrefix = "amdgcn" in {
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defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_amdgcn_workitem_id">;
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defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz <
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"__builtin_amdgcn_workgroup_id">;
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def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">,
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Intrinsic<[], [], [IntrConvergent]>;
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def int_amdgcn_div_scale : Intrinsic<
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// 1st parameter: Numerator
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// 2nd parameter: Denominator
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// 3rd parameter: Constant to select select between first and
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// second. (0 = first, 1 = second).
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[llvm_anyfloat_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
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[IntrNoMem]
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>;
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def int_amdgcn_div_fmas : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
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[IntrNoMem]
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>;
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def int_amdgcn_div_fixup : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]
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>;
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def int_amdgcn_trig_preop : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
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>;
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def int_amdgcn_sin : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_cos : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_log_clamp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_rcp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_rsq : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_rsq_clamp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_amdgcn_ldexp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
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>;
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def int_amdgcn_class : Intrinsic<
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[llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubema : GCCBuiltin<"__builtin_amdgcn_cubema">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubesc : GCCBuiltin<"__builtin_amdgcn_cubesc">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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class AMDGPUImageLoad : Intrinsic <
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[llvm_v4f32_ty], // vdata(VGPR)
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[llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty], // slc(imm)
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[IntrReadMem]>;
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def int_amdgcn_image_load : AMDGPUImageLoad;
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def int_amdgcn_image_load_mip : AMDGPUImageLoad;
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class AMDGPUImageStore : Intrinsic <
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[],
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[llvm_v4f32_ty, // vdata(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty], // slc(imm)
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[]>;
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def int_amdgcn_image_store : AMDGPUImageStore;
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def int_amdgcn_image_store_mip : AMDGPUImageStore;
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class AMDGPUImageAtomic : Intrinsic <
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[llvm_i32_ty],
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[llvm_i32_ty, // vdata(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty], // slc(imm)
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[]>;
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def int_amdgcn_image_atomic_swap : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_add : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_sub : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_smin : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_umin : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_smax : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_umax : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_and : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_or : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_xor : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_inc : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_dec : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_cmpswap : Intrinsic <
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[llvm_i32_ty],
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[llvm_i32_ty, // src(VGPR)
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llvm_i32_ty, // cmp(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty], // slc(imm)
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[]>;
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def int_amdgcn_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <
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"__builtin_amdgcn_read_workdim">;
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def int_amdgcn_buffer_wbinvl1_sc :
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GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">,
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Intrinsic<[], [], []>;
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def int_amdgcn_buffer_wbinvl1 :
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GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">,
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Intrinsic<[], [], []>;
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def int_amdgcn_s_dcache_inv :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">,
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Intrinsic<[], [], []>;
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def int_amdgcn_s_memtime :
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GCCBuiltin<"__builtin_amdgcn_s_memtime">,
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Intrinsic<[llvm_i64_ty], [], []>;
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def int_amdgcn_s_sleep :
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GCCBuiltin<"__builtin_amdgcn_s_sleep">,
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Intrinsic<[], [llvm_i32_ty], []> {
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}
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def int_amdgcn_dispatch_ptr :
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GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">,
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Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], [IntrNoMem]>;
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// __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
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def int_amdgcn_interp_p1 :
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GCCBuiltin<"__builtin_amdgcn_interp_p1">,
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Intrinsic<[llvm_float_ty],
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[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>; // This intrinsic reads from lds, but the memory
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// values are constant, so it behaves like IntrNoMem.
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// __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
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def int_amdgcn_interp_p2 :
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GCCBuiltin<"__builtin_amdgcn_interp_p2">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>; // See int_amdgcn_v_interp_p1 for why this is
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// IntrNoMem.
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def int_amdgcn_mbcnt_lo :
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GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_amdgcn_mbcnt_hi :
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GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// CI+ Intrinsics
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//===----------------------------------------------------------------------===//
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def int_amdgcn_s_dcache_inv_vol :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">,
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Intrinsic<[], [], []>;
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def int_amdgcn_buffer_wbinvl1_vol :
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GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">,
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Intrinsic<[], [], []>;
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//===----------------------------------------------------------------------===//
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// VI Intrinsics
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//===----------------------------------------------------------------------===//
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// llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <bound_ctrl> <bank_mask> <row_mask>
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def int_amdgcn_mov_dpp :
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Intrinsic<[llvm_anyint_ty],
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[LLVMMatchType<0>, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty,
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llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
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def int_amdgcn_s_dcache_wb :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">,
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Intrinsic<[], [], []>;
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def int_amdgcn_s_dcache_wb_vol :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">,
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Intrinsic<[], [], []>;
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def int_amdgcn_s_memrealtime :
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GCCBuiltin<"__builtin_amdgcn_s_memrealtime">,
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Intrinsic<[llvm_i64_ty], [], []>;
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// llvm.amdgcn.ds.permute <index> <src>
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def int_amdgcn_ds_permute :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
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// llvm.amdgcn.ds.bpermute <index> <src>
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def int_amdgcn_ds_bpermute :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
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}
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