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4c4a37be92
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which uses v4f16 and v8f16 vector operands and return values. All the moving parts are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16 intrinsic. In a follow-up patch the rest of the intrinsics and tests will be added. Differential Revision: https://reviews.llvm.org/D44538 llvm-svn: 327839
40 lines
1.6 KiB
LLVM
40 lines
1.6 KiB
LLVM
; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-HARD
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; RUN: llc < %s -mtriple=armeb-none-eabi -mattr=+v8.2a,+fullfp16,+neon -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-HARD-BE
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+v8.2a,+fullfp16,+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP
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; RUN: llc < %s -mtriple=armeb-none-eabi -mattr=+v8.2a,+fullfp16,+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-BE
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declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
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define dso_local <8 x half> @t_vabsq_f16(<8 x half> %a) {
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; CHECK-LABEL: t_vabsq_f16:
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; CHECK-HARD: vabs.f16 q0, q0
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; CHECK-HARD-NEXT: bx lr
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; CHECK-HARD-BE: vrev64.16 [[Q8:q[0-9]+]], q0
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; CHECK-HARD-BE-NEXT: vabs.f16 [[Q8]], [[Q8]]
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; CHECK-HARD-BE-NEXT: vrev64.16 q0, [[Q8]]
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; CHECK-HARD-BE-NEXT: bx lr
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; CHECK-SOFTFP: vmov d{{.*}}, r2, r3
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; CHECK-SOFTFP: vmov d{{.*}}, r0, r1
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; CHECK-SOFTFP: vabs.f16 q{{.*}}, q{{.*}}
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; CHECK-SOFTFP: vmov r0, r1, d{{.*}}
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; CHECK-SOFTFP: vmov r2, r3, d{{.*}}
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; CHECK-SOFTFP: bx lr
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; CHECK-SOFTFP-BE: vmov [[D17:d[0-9]+]], r3, r2
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; CHECK-SOFTFP-BE: vmov [[D16:d[0-9]+]], r1, r0
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; CHECK-SOFTFP-BE: vrev64.16 [[Q8:q[0-9]+]], [[Q8]]
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; CHECK-SOFTFP-BE: vabs.f16 [[Q8]], [[Q8]]
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; CHECK-SOFTFP-BE: vrev64.16 [[Q8]], [[Q8]]
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; CHECK-SOFTFP-BE: vmov r1, r0, [[D16]]
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; CHECK-SOFTFP-BE: vmov r3, r2, [[D17]]
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; CHECK-SOFTFP-BE: bx lr
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entry:
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%vabs1.i = tail call <8 x half> @llvm.fabs.v8f16(<8 x half> %a) #3
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ret <8 x half> %vabs1.i
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}
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