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9ea26aa436
When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can decide that the result is OK (v1i64 is legal on AArch64, for example) but it still need scalarising because of that v1i1. There was no code to do this though. AArch64 and ARM64 have DAG combines to produce efficient code and prevent that occuring in *most* such situations, but there are edge cases that they miss. This adds a legalization to cope with that. llvm-svn: 205626
75 lines
2.5 KiB
LLVM
75 lines
2.5 KiB
LLVM
; RUN: llc %s -o - -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s
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; This is the analogue of AArch64's file of the same name. It's mostly testing
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; some form of correct lowering occurs, the tests are a little artificial but I
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; strongly suspect there's room for improved CodeGen (FIXME).
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define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
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; CHECK-LABEL: test_sext_extr_cmp_0:
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; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: csinc
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%1 = icmp sge <1 x i64> %v1, %v2
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%2 = extractelement <1 x i1> %1, i32 0
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%vget_lane = sext i1 %2 to i64
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ret i64 %vget_lane
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}
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define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) {
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; CHECK-LABEL: test_sext_extr_cmp_1:
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; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
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%1 = fcmp oeq <1 x double> %v1, %v2
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%2 = extractelement <1 x i1> %1, i32 0
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%vget_lane = sext i1 %2 to i64
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ret i64 %vget_lane
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}
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define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
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; CHECK-LABEL: test_select_v1i1_0:
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; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%1 = icmp eq <1 x i64> %v1, %v2
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%res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
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ret <1 x i64> %res
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}
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define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) {
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; CHECK-LABEL: test_select_v1i1_1:
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; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%1 = fcmp oeq <1 x double> %v1, %v2
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%res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
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ret <1 x i64> %res
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}
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define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) {
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; CHECK-LABEL: test_select_v1i1_2:
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; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%1 = icmp eq <1 x i64> %v1, %v2
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%res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v3
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ret <1 x double> %res
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}
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define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) {
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; CHECK-LABEL: test_select_v1i1_3:
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; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
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%tst = icmp eq i64 %lhs, %rhs
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%evil = insertelement <1 x i1> undef, i1 %tst, i32 0
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%res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3
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ret <1 x i64> %res
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}
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define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) {
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; CHECK-LABEL: test_br_extr_cmp:
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; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}}
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%1 = icmp eq <1 x i64> %v1, %v2
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%2 = extractelement <1 x i1> %1, i32 0
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br i1 %2, label %if.end, label %if.then
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if.then:
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ret i32 0;
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if.end:
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ret i32 1;
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}
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