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legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 llvm-svn: 120501
66 lines
1.7 KiB
LLVM
66 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=armv6-apple-darwin -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6
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; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF
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@t = weak global i32 ()* null ; <i32 ()**> [#uses=1]
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declare void @g(i32, i32, i32, i32)
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define void @t1() {
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; CHECKELF: t1:
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; CHECKELF: bl g(PLT)
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call void @g( i32 1, i32 2, i32 3, i32 4 )
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ret void
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}
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define void @t2() {
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; CHECKV6: t2:
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; CHECKV6: bx r0 @ TAILCALL
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%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
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%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
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ret void
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}
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define void @t3() {
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; CHECKV6: t3:
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; CHECKV6: b _t2 @ TAILCALL
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; CHECKELF: t3:
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; CHECKELF: b t2(PLT) @ TAILCALL
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tail call void @t2( ) ; <i32> [#uses=0]
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ret void
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}
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; Sibcall optimization of expanded libcalls. rdar://8707777
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define double @t4(double %a) nounwind readonly ssp {
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entry:
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; CHECKV6: t4:
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; CHECKV6: b _sin @ TAILCALL
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; CHECKELF: t4:
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; CHECKELF: b sin(PLT) @ TAILCALL
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%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
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ret double %0
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}
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define float @t5(float %a) nounwind readonly ssp {
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entry:
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; CHECKV6: t5:
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; CHECKV6: b _sinf @ TAILCALL
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; CHECKELF: t5:
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; CHECKELF: b sinf(PLT) @ TAILCALL
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%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
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ret float %0
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}
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declare float @sinf(float) nounwind readonly
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declare double @sin(double) nounwind readonly
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define i32 @t6(i32 %a, i32 %b) nounwind readnone {
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entry:
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; CHECKV6: t6:
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; CHECKV6: b ___divsi3 @ TAILCALL
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; CHECKELF: t6:
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; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL
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%0 = sdiv i32 %a, %b
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ret i32 %0
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}
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